📄 fpga_core.srr
字号:
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fpga_core|clk_48 100.0 MHz 52.4 MHz 10.000 19.079 -9.079 inferred Inferred_clkgroup_0
fpga_core|clk_54 100.0 MHz 49.2 MHz 10.000 20.338 -10.338 inferred Inferred_clkgroup_1
=========================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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fpga_core|clk_48 fpga_core|clk_48 | 10.000 -9.079 | No paths - | No paths - | No paths -
fpga_core|clk_48 fpga_core|clk_54 | Diff grp - | No paths - | No paths - | No paths -
fpga_core|clk_54 fpga_core|clk_48 | Diff grp - | No paths - | No paths - | No paths -
fpga_core|clk_54 fpga_core|clk_54 | 10.000 -10.338 | No paths - | No paths - | No paths -
============================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: fpga_core|clk_48
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------
fifo_data_inst.DFN1P0_EMPTY fpga_core|clk_48 DFN1P0 Q empty 0.483 -9.079
ren fpga_core|clk_48 DFN1P0 Q ren 0.483 -8.624
fifo_data_inst.DFN1C0_WGRYSYNC_9_inst fpga_core|clk_48 DFN1C0 Q WGRYSYNC_9_net 0.483 -7.644
fifo_data_inst.DFN1C0_WGRYSYNC_10_inst fpga_core|clk_48 DFN1C0 Q WGRYSYNC_10_net 0.483 -7.536
fifo_data_inst.DFN1C0_WGRYSYNC_11_inst fpga_core|clk_48 DFN1C0 Q WGRYSYNC_11_net 0.483 -7.518
fifo_data_inst.DFN1C0_RBIN_1_inst fpga_core|clk_48 DFN1C0 Q RBIN_1_net 0.483 -6.733
fifo_data_inst.DFN1C0_RBIN_0_inst fpga_core|clk_48 DFN1C0 Q RBIN_0_net 0.483 -6.690
fifo_data_inst.DFN1C0_RBIN_2_inst fpga_core|clk_48 DFN1C0 Q RBIN_2_net 0.483 -6.548
fifo_data_inst.DFN1C0_RBIN_3_inst fpga_core|clk_48 DFN1C0 Q RBIN_3_net 0.483 -6.481
fifo_data_inst.DFN1C0_WGRYSYNC_6_inst fpga_core|clk_48 DFN1C0 Q WGRYSYNC_6_net 0.483 -6.454
=========================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------------------
fifo_data_inst.DFN1P0_EMPTY fpga_core|clk_48 DFN1P0 D AOI1_0_Y 9.590 -9.079
fifo_data_inst.DFN1C0_RGRY_8_inst fpga_core|clk_48 DFN1C0 D XOR2_80_Y 9.690 -1.514
fifo_data_inst.DFN1C0_RGRY_6_inst fpga_core|clk_48 DFN1C0 D XOR2_96_Y 9.690 -1.328
fifo_data_inst.DFN1C0_RGRY_9_inst fpga_core|clk_48 DFN1C0 D XOR2_57_Y 9.590 -1.240
fifo_data_inst.DFN1C0_RGRY_7_inst fpga_core|clk_48 DFN1C0 D XOR2_22_Y 9.590 -1.055
fifo_data_inst.DFN1C0_RGRY_10_inst fpga_core|clk_48 DFN1C0 D XOR2_110_Y 9.590 -0.904
fifo_data_inst.DFN1E1C0_MEM_RADDR_10_inst fpga_core|clk_48 DFN1E1C0 D XOR3_9_Y 9.590 -0.828
fifo_data_inst.DFN1C0_RGRY_5_inst fpga_core|clk_48 DFN1C0 D XOR2_105_Y 9.690 -0.615
fifo_data_inst.DFN1C0_RBIN_9_inst fpga_core|clk_48 DFN1C0 D RBINNXT_9_net 9.690 -0.544
fifo_data_inst.DFN1C0_RGRY_4_inst fpga_core|clk_48 DFN1C0 D XOR2_88_Y 9.690 -0.424
=============================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 18.669
= Slack (non-critical) : -9.079
Number of logic level(s): 18
Starting point: fifo_data_inst.DFN1P0_EMPTY / Q
Ending point: fifo_data_inst.DFN1P0_EMPTY / D
The start point is clocked by fpga_core|clk_48 [rising] on pin CLK
The end point is clocked by fpga_core|clk_48 [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
fifo_data_inst.DFN1P0_EMPTY DFN1P0 Q Out 0.483 0.483 -
empty Net - - 0.469 - 2
fifo_data_inst.NAND2_1 NAND2 A In - 0.953 -
fifo_data_inst.NAND2_1 NAND2 Y Out 0.389 1.342 -
NAND2_1_Y Net - - 0.279 - 1
fifo_data_inst.AND2_MEMORYRE NOR2A A In - 1.621 -
fifo_data_inst.AND2_MEMORYRE NOR2A Y Out 0.466 2.087 -
MEMORYRE Net - - 1.178 - 6
fifo_data_inst.AND2_40 AND2 B In - 3.264 -
fifo_data_inst.AND2_40 AND2 Y Out 0.466 3.730 -
AND2_40_Y Net - - 0.469 - 2
fifo_data_inst.AO1_14 AO1 B In - 4.199 -
fifo_data_inst.AO1_14 AO1 Y Out 0.434 4.634 -
AO1_14_Y Net - - 0.655 - 3
fifo_data_inst.AO1_43 AO1 B In - 5.289 -
fifo_data_inst.AO1_43 AO1 Y Out 0.434 5.723 -
AO1_43_Y Net - - 0.841 - 4
fifo_data_inst.AO1_49 AO1 B In - 6.564 -
fifo_data_inst.AO1_49 AO1 Y Out 0.434 6.998 -
AO1_49_Y Net - - 0.469 - 2
fifo_data_inst.AO1_62 AO1 B In - 7.467 -
fifo_data_inst.AO1_62 AO1 Y Out 0.434 7.902 -
AO1_62_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 B In - 8.181 -
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 Y Out 0.691 8.871 -
RBINNXT_7_net Net - - 1.178 - 6
fifo_data_inst.XOR2_5 XNOR2 A In - 10.049 -
fifo_data_inst.XOR2_5 XNOR2 Y Out 0.366 10.415 -
XOR2_5_Y Net - - 0.469 - 2
fifo_data_inst.AND2_94 AND2 A In - 10.884 -
fifo_data_inst.AND2_94 AND2 Y Out 0.389 11.273 -
AND2_94_Y Net - - 0.469 - 2
fifo_data_inst.AO1_54 AO1 A In - 11.743 -
fifo_data_inst.AO1_54 AO1 Y Out 0.390 12.133 -
AO1_54_Y Net - - 0.279 - 1
fifo_data_inst.AO1_17 AO1 C In - 12.412 -
fifo_data_inst.AO1_17 AO1 Y Out 0.482 12.894 -
AO1_17_Y Net - - 0.469 - 2
fifo_data_inst.AO1_28 AO1 B In - 13.363 -
fifo_data_inst.AO1_28 AO1 Y Out 0.434 13.797 -
AO1_28_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 B In - 14.076 -
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 Y Out 0.691 14.767 -
RDIFF_10_net Net - - 0.841 - 4
fifo_data_inst.XNOR2_33 XNOR2 B In - 15.608 -
fifo_data_inst.XNOR2_33 XNOR2 Y Out 0.691 16.298 -
XNOR2_33_Y Net - - 0.279 - 1
fifo_data_inst.AND2_95 AND2 B In - 16.577 -
fifo_data_inst.AND2_95 AND2 Y Out 0.466 17.043 -
AND2_95_Y Net - - 0.279 - 1
fifo_data_inst.AO1_3 AO1 A In - 17.322 -
fifo_data_inst.AO1_3 AO1 Y Out 0.390 17.712 -
AO1_3_Y Net - - 0.279 - 1
fifo_data_inst.AOI1_0 AOI1 C In - 17.991 -
fifo_data_inst.AOI1_0 AOI1 Y Out 0.398 18.390 -
AOI1_0_Y Net - - 0.279 - 1
fifo_data_inst.DFN1P0_EMPTY DFN1P0 D In - 18.669 -
===================================================================================================
Total path delay (propagation time + setup) of 19.079 is 9.340(49.0%) logic and 9.739(51.0%) route.
Path information for path number 2:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 18.653
= Slack (non-critical) : -9.063
Number of logic level(s): 18
Starting point: fifo_data_inst.DFN1P0_EMPTY / Q
Ending point: fifo_data_inst.DFN1P0_EMPTY / D
The start point is clocked by fpga_core|clk_48 [rising] on pin CLK
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