fpga_core.srr

可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":768:9:768:15|Pruning instance AND2_39 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":654:9:654:14|Pruning instance AND2_9 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":642:9:642:16|Pruning instance AND2_115 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":637:9:637:15|Pruning instance XOR2_27 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":631:9:631:15|Pruning instance AND2_19 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":622:9:622:15|Pruning instance AND2_64 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":599:10:599:17|Pruning instance XNOR3_13 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":598:9:598:15|Pruning instance AND2_44 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":542:8:542:13|Pruning instance AO1_42 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":538:10:538:17|Pruning instance XNOR3_20 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":493:9:493:15|Pruning instance AND2_76 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":492:9:492:15|Pruning instance AND2_16 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":472:9:472:14|Pruning instance AND2_4 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":471:9:471:14|Pruning instance DFN1_3 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":445:9:445:15|Pruning instance XOR2_20 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":444:9:444:15|Pruning instance AND2_71 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":441:9:441:15|Pruning instance XOR2_18 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":439:9:439:15|Pruning instance AND2_90 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":418:9:418:16|Pruning instance AND2_111 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":404:9:404:15|Pruning instance AND2_38 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":399:9:399:15|Pruning instance AND2_77 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":398:9:398:16|Pruning instance AND2_114 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":371:9:371:15|Pruning instance AND2_99 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":326:9:326:15|Pruning instance AND2_32 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":311:9:311:15|Pruning instance AND2_78 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":308:9:308:15|Pruning instance AND2_18 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":294:9:294:15|Pruning instance AND2_96 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":278:10:278:17|Pruning instance XNOR3_15 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":267:9:267:15|Pruning instance AND2_69 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":252:8:252:13|Pruning instance AO1_22 - not in use ...

@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":247:9:247:15|Pruning instance AND2_23 - not in use ...

@N: CG364 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":13:7:13:15|Synthesizing module fpga_core

@W: CL169 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":154:2:154:7|Pruning Register ctrl1 

@W: CL169 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":154:2:154:7|Pruning Register ctrl5 

@W: CL169 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":154:2:154:7|Pruning Register ctrl2 

@W: CL169 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":154:2:154:7|Pruning Register ctrl6 

@W: CL169 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":154:2:154:7|Pruning Register ctrl0 

@W: CL169 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":104:2:104:7|Pruning Register state[4:0] 

@W: CL190 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":225:2:225:7|Optimizing register bit count_r[0] to a constant 0
@W: CL171 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":225:2:225:7|Pruning Register bit <0> of count_r[9:0] 

@W: CL159 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":35:20:35:27|Input usb_flag is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 07 16:22:44 2008

###########################################################]
Synplicity Proasic Technology Mapper, Version 8.8.0, Build 015R, Built Apr 15 2007 16:31:14
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8A1
@N: MF249 |Running in 32-bit mode.


Automatic dissolve at startup in view:work.fpga_core(verilog) of fifo_data_inst(fifo_fpga1280x8)
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 42MB)
@N:"h:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":154:2:154:7|Found counter in view:work.fpga_core(verilog) inst count_w[10:0]
@N: MF238 :"h:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":239:17:239:28|Found 9 bit incrementor, 'un6_count_r_1[9:1]'

Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
@W|Although I/O insertion is disabled, Inferring tristate/bidirectional IO buffer to compensate device without internal tristate cell. 

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 42MB peak: 42MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 41MB peak: 42MB)

Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 42MB peak: 43MB)

High Fanout Net Report
**********************

Driver Instance / Pin Name          Fanout, notes                 
------------------------------------------------------------------
RESET / RESET                       28 : 28 asynchronous set/reset
reset / reset                       118                           
fifo_data_inst.DFN1C0_DVLDI / Q     16                            
fifo_data_inst.DFN1_1 / Q           16                            
fifo_data_inst.DFN1_0 / Q           16                            
ren_i / Y                           16                            
==================================================================

Replicating Combinational Instance ren_i, fanout 16 segments 2
Buffering fifo_data_inst.DFN1_0_Q, fanout 16 segments 2
Buffering fifo_data_inst.DFN1_1_Q, fanout 16 segments 2
Buffering fifo_data_inst.DVLDI, fanout 16 segments 2

Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 41MB peak: 43MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 42MB peak: 43MB)

Added 3 Buffers
Added 1 Cells via replication
	Added 0 Sequential Cells via replication
	Added 1 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 42MB peak: 43MB)
Writing Analyst data base H:\fpga_test\fpga_fifo_0122_02\synthesis\fpga_core.srm
@N: BN225 |Writing default property annotation file H:\fpga_test\fpga_fifo_0122_02\synthesis\fpga_core.map.
Writing EDIF Netlist and constraint files
Found clock fpga_core|clk_54 with period 10.00ns 
Found clock fpga_core|clk_48 with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed May 07 16:22:48 2008
#


Top view:               fpga_core
Library name:           PA3
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.40, P = 1.33, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        PA3
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -10.338

                     Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock       Frequency     Frequency     Period        Period        Slack       Type         Group