ctr_data_tb.v

可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序

// ctr_data.v
`timescale  1ns/100ps

module ctr_data_tb( );
  reg tb_reset;
  reg tb_frame_valid;
  reg tb_line_valid;
  reg tb_powerdown;
  reg tb_usb_flag;

  reg[7:0] tb_datain;
  reg wen;
  reg ren;
    
  reg [10:0] waddr;
  reg [9 :0] raddr;
  
  reg [1:0] state;
  reg [1:0] idle;
  reg [1:0] wait_work;
  reg [1:0] work;
  reg [1:0] clear;
  
  reg tb_clk_54;
  reg tb_clk_48;
  

    fpga_core   fpga_core_inst
         (  
         .clk_54       (tb_clk_54),
         .clk_48       (tb_clk_48),
         .data_out     (         ),
         .datain       (tb_datain),
         .reset        (tb_reset),
         .frame_valid  (tb_frame_valid),
         .line_valid   (tb_line_valid),
         .usb_flag     (tb_usb_flag),
         .powerdown    (tb_powerdown)        
         );
 
      
  always  
       begin 
        # 9;  
        tb_clk_54 =1;
        
        # 9; 
         tb_clk_54 =0;
         end
        
  always  begin 
        # 10; 
        tb_clk_48 =1;

        # 10; 
        tb_clk_48 =0;
        end 
 
 //----------------------------
   task write_data;
    input enable;
    input data;
    input waddr1;
   begin 
    @(posedge tb_clk_54)
    wen <= enable; 
    tb_datain<=data;
    waddr <=waddr1;
    end
    endtask  


 task read_data;
   input enable1;
   input raddr1;
  begin
    @(posedge tb_clk_48)
     ren <= enable1;
     raddr <=raddr1;
     end
     endtask
     
  initial begin 
      tb_reset =0;
   # 100;
      tb_reset =1;
      tb_usb_flag = 1;
      tb_powerdown = 0;
   #  50; 
       write_data(1'b0,8'h12,11'h0);
       write_data(1'b0,8'h15,11'h64);
       write_data(1'b0,8'h16,11'h65);  
       write_data(1'b0,8'h10,11'h50); 
       write_data(1'b0,8'h63,11'h128);
       write_data(1'b1,8'h64,11'h129); 
       write_data(1'b0,8'h77,11'h33E);
       write_data(1'b1,8'h78,11'h33F); 
       write_data(1'b0,8'h88,11'h334); 
  #  20;
       read_data(1'b0,10'h32);
       read_data(1'b0,10'h64);
       read_data(1'b0,10'h13B);
       
       
  # 3000;
	$display("simulution finish");
	$stop; 

      end
      


   endmodule