_primary.vhd

来自「可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除6」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity fifo_fpga is
    port(
        WD              : in     vl_logic_vector(7 downto 0);
        RD              : out    vl_logic_vector(15 downto 0);
        WEN             : in     vl_logic;
        REN             : in     vl_logic;
        WADDR           : in     vl_logic_vector(10 downto 0);
        RADDR           : in     vl_logic_vector(9 downto 0);
        WCLK            : in     vl_logic;
        RCLK            : in     vl_logic;
        RESET           : in     vl_logic
    );
end fifo_fpga;