_primary.vhd

来自「可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除6」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity fifo_fpga1280x8 is
    port(
        DATA            : in     vl_logic_vector(7 downto 0);
        DATAOUT         : out    vl_logic_vector(15 downto 0);
        WE              : in     vl_logic;
        RE              : in     vl_logic;
        WCLOCK          : in     vl_logic;
        RCLOCK          : in     vl_logic;
        FULL            : out    vl_logic;
        EMPTY           : out    vl_logic;
        RESET           : in     vl_logic
    );
end fifo_fpga1280x8;