_info

可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序

m255
13
cModel Technology
dH:\fpga_test\test\new\simulation
vctr_data_tb
Ic7P3ON9>;YHeX[jcAB@kQ1
VVWO5l:XYH>TNPOY7[jdff3
dH:\fpga_test\fpga_fifo_0122_02\simulation
w1200625650
8H:/fpga_test/fpga_fifo_0122_02/stimulus/ctr_data_tb.v
FH:/fpga_test/fpga_fifo_0122_02/stimulus/ctr_data_tb.v
L0 4
VVWO5l:XYH>TNPOY7[jdff3
OW;L;6.2g;35
r1
31
o+incdir+H:/fpga_test/fpga_fifo_0122_02/stimulus +incdir+H:/fpga_test/fpga_fifo_0122_02/hdl -work presynth -O0
vfifo_fpga
INF<ENSjYnbd=jh:b?KICC1
V99`@I_Fk3Z^]W[Xl:_FLX2
w1199950932
8H:/fpga_test/test/new/smartgen/fifo_fpga/fifo_fpga.v
FH:/fpga_test/test/new/smartgen/fifo_fpga/fifo_fpga.v
L0 5
V99`@I_Fk3Z^]W[Xl:_FLX2
OW;L;6.2g;35
r1
31
o+incdir+H:/fpga_test/test/new/smartgen/fifo_fpga +incdir+H:/fpga_test/test/new/hdl -work presynth -O0
vfifo_fpga1280x8
Ik@^fnhcEno0dNMBeciXnL1
V^9Y4:f@Fi=38aXXd9=D343
dH:\fpga_test\fpga_fifo_0122_02\simulation
w1200540588
8H:/fpga_test/fpga_fifo_0122_02/smartgen/fifo_fpga1280x8/fifo_fpga1280x8.v
FH:/fpga_test/fpga_fifo_0122_02/smartgen/fifo_fpga1280x8/fifo_fpga1280x8.v
L0 5
V^9Y4:f@Fi=38aXXd9=D343
OW;L;6.2g;35
r1
31
o+incdir+H:/fpga_test/fpga_fifo_0122_02/smartgen/fifo_fpga1280x8 +incdir+H:/fpga_test/fpga_fifo_0122_02/hdl -work presynth -O0
vfpga_core
I=W?I3abV@ODmXH_<dTBEj0
VY<Qg4J4=b_lz6ci4jZ<@O1
dH:\fpga_test\fpga_fifo_0122_02\simulation
w1201006956
8H:/fpga_test/fpga_fifo_0122_02/hdl/fifo_fpga_1280x8.v
FH:/fpga_test/fpga_fifo_0122_02/hdl/fifo_fpga_1280x8.v
L0 13
VY<Qg4J4=b_lz6ci4jZ<@O1
OW;L;6.2g;35
r1
31
o+incdir+H:/fpga_test/fpga_fifo_0122_02/hdl +incdir+H:/fpga_test/fpga_fifo_0122_02/hdl -work presynth -O0
vfpga_core_tb
Ih0VGQ]SZV3Z9eVjHJ1NeM2
Vfb[U637WEmgYdF?3ETemm1
dE:\fpga_test\new\new\new\simulation
w1201007469
8E:/fpga_test/new/new/new/stimulus/fpga_core_tb.v
FE:/fpga_test/new/new/new/stimulus/fpga_core_tb.v
L0 5
Vfb[U637WEmgYdF?3ETemm1
OW;L;6.2g;35
r1
31
o+incdir+E:/fpga_test/new/new/new/stimulus +incdir+E:/fpga_test/new/new/new/hdl -work presynth -O0
vfpga_fpga_1280x8_tb
I@L_U45=T?;[cZ4Y9R2REL1
VBYSbFF6o7@R9bKWF2a52>3
dH:\fpga_test\fpga_fifo_0122_02\simulation
w1210151738
8H:/fpga_test/fpga_fifo_0122_02/stimulus/fifo_fpga_1280x8_tb.v
FH:/fpga_test/fpga_fifo_0122_02/stimulus/fifo_fpga_1280x8_tb.v
L0 5
VBYSbFF6o7@R9bKWF2a52>3
OW;L;6.2g;35
r1
31
o+incdir+H:/fpga_test/fpga_fifo_0122_02/stimulus +incdir+H:/fpga_test/fpga_fifo_0122_02/hdl -work presynth -O0