clk_pll.gen

可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序

Version:8.0.0.40
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_PLL_STATIC
LPM_HINT:NONE
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
"DESDIR:E:/fpga_test/new/new/new/smartgen\clk_pll"
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IS4X2M1
SMARTGEN_PACKAGE:pq208
FIN:40.000000
CLKASRC:1
FBDLY:1
FBMUX:1
XDLYSEL:0
PRIMFREQ:54.000000
PPHASESHIFT:0
DLYAVAL:1
OAMUX:4
SEC1FREQ:48.000000
UGLB:1
UYB:0
GLBDLYVAL:1
YBDLYVAL:1
S1PHASESHIFT:0
OBMUX:2
SEC2FREQ:350.000000
UGLC:1
UYC:0
GLCDLYVAL:1
YCDLYVAL:1
S2PHASESHIFT:0
OCMUX:2
POWERDOWN_POLARITY:0
LOCK_POLARITY:1