div5.v

来自「简单的VERILOG五分频电路描述」· Verilog 代码 · 共 48 行

 /*主模块*/                                  /*测试模块*/
module div5(rst,clk,out5);                   `timescale 1ns/1ns                                
input clk,rst;                               module div5_tb;                             
output out5;                                 reg clk,rst;                                
wire clk,rst,nclk;                           wire out5;                                  
reg[2:0] count1,count2;                      div5 div5(.rst(rst),.clk(clk),.out5(out5)); 
reg temp1,temp2;                             initial                                     
assign nclk=~clk;                            begin                                       
always@(negedge clk or posedge rst)          clk=0;                                      
if(!rst)//占空比为4：6信号的产生             rst=0;                                      
	begin                                      #10                                         
	temp1<=0;	count1<=3'd0;	count2<=3'd0;      rst=1;                                      
	end                                        end                                         
else                                         always #10 clk=~clk;//产生周期为20单位的时钟
	begin                                      endmodule                                   
count1<=count1+1; //计数器   
if(count1==3'd2)//3个周期后信号翻转为1
 begin   temp1<=1;   end
 else if(count1==3'd4)//2个周期后信号翻转为0
 begin  count1<=3'd0; temp1<=0; end  
end        
always@(negedge nclk or posedge rst)  
if(!rst)
	begin
		temp2<=0;
		count2<=3'd0;
	end
else	begin    count2<=count2+1;
	 if(count2==3'd2)
     begin      temp2<=1;    end
   else if(count2==3'd4)
     begin
     count2<=3'd0;
     temp2<=0;
     end  
end                                                                               
assign out5=temp1|temp2;   //产生输出
endmodule