clk_div.v

FPGA驱动STN （16x2）的程序

`timescale 1ns / 100ps
module clk_div(
               //input port
               clk_in, // 50Mhz
               rst_n,
               //output port
               clk_out // 1s
);
//input signal 
input          clk_in;
input          rst_n;
//output signal
output         clk_out;
//internal
reg            clk_out;
reg [9:0]      count1;
reg [9:0]      count2;
reg [5:0]      count3;
reg            clk_dly1;
reg            clk_dly2;
//
parameter      DLY = 1;
//-----------------------main code----------------------------
always @(posedge clk_in or negedge rst_n)
begin
	if(!rst_n)
	  count1 <= #DLY 10'b00000_00000;
	else if(count1 == 10'b11111_01000) // 1000
	  count1 <= #DLY 10'b00000_00000;
	else
	  count1 <= #DLY count1 + 1'b1;
end

always @(posedge clk_in or negedge rst_n)
begin
	if(!rst_n)
	  clk_dly1 <= #DLY 1'b0;
	else if(count1 == 10'b11111_01000) // 1000
	  clk_dly1 <= #DLY ~clk_dly1;
	else
	  clk_dly1 <= #DLY clk_dly1; 
end

always @(posedge clk_dly1 or negedge rst_n)        
begin                                         
	if(!rst_n)                                  
	  count2 <= #DLY 10'b00000_00000;           
	else if(count2 == 10'b11111_01000) // 1000  
	  count2 <= #DLY 10'b00000_00000;           
	else                                        
	  count2 <= #DLY count2 + 1'b1;             
end          

always @(posedge clk_dly1 or negedge rst_n)                                         
begin                                         
	if(!rst_n)                                   
	  clk_dly2 <= #DLY 1'b0;                    
	else if(count2 == 10'b11111_01000) // 1000  
	  clk_dly2 <= #DLY ~clk_dly2;               
	else                                        
	  clk_dly2 <= #DLY clk_dly2;                
end             

always @(posedge clk_dly2 or negedge rst_n)                                  
begin                                          
	if(!rst_n)                                   
	  count3 <= #DLY 6'b000_000;            
	else if(count3 == 6'b00_011) // 3   
	  count3 <= #DLY 6'b000_000;            
	else                                         
	  count3 <= #DLY count3 + 1'b1;              
end      

always @(posedge clk_dly2 or negedge rst_n)                                         
begin                                         
	if(!rst_n)                                   
	  clk_out <= #DLY 1'b0;                    
	else if(count3 == 6'b00_011) // 3 
	  clk_out <= #DLY ~clk_out;               
	else                                        
	  clk_out <= #DLY clk_out;                
end                        

endmodule