lcd_contral.v

FPGA驱动STN （16x2）的程序

// project: LCD DISPLAY
// author : PanWenrong
// time   : 9/6/2007
// version number : 1
`timescale 1ns / 100ps
module lcd_control(
                   // input port
                   clk, // 1s
                   rst_n,
                   // out port
                   lcd_e,
                   lcd_rs,
                   lcd_rw,
                   lcd_data 
);
// input signal
input              clk;
input              rst_n;
// output signal
output             lcd_e;
output             lcd_rs;
output             lcd_rw;
output [7:0]       lcd_data;
//--------state machine--------
parameter  idle = 12'b000000_000001;
parameter   st1 = 12'b000000_000010;
parameter   st2 = 12'b000000_000100; 
parameter   st3 = 12'b000000_001000;
parameter   st4 = 12'b000000_010000;
parameter   st5 = 12'b000000_100000;
parameter   st6 = 12'b000001_000000;
parameter   st7 = 12'b000010_000000;
parameter   st8 = 12'b000100_000000;
parameter   st9 = 12'b001000_000000;
parameter  st10 = 12'b010000_000000;
//parameter  st11 = 12'b100000_000000;
//-------internal signal--------
reg        lcd_e;      
reg        lcd_rs;    
reg        lcd_rw;    
reg [7:0]  lcd_data;  
reg [4:0]  count;
reg [11:0] current_state;
reg [11:0] next_state;
//
parameter  DLY = 1;
//-------main code-------
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	  count <= #DLY 5'b00000;
	else if(count == 5'b10111) // count == 23
	  count <= #DLY 5'b00000;
	else
	  count <= #DLY count + 1'b1;
end

always @(clk or rst_n)
begin
	if(!rst_n)
	  lcd_e = 1'b0;
	else 
	  lcd_e = clk; // when lcd_e negedge lcd work
end
//----------state machine----------
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	  current_state <= #DLY idle;
	else
	  current_state <= #DLY next_state;
end

always @(current_state or count)
begin
	case(current_state)
	  idle: 
	      if(count == 5'b00011) // 3
	        next_state = st1;
	      else
	        next_state = idle;
	  st1:
	      if(count == 5'b00100) // 4
	        next_state = st2;
	      else 
	        next_state = st1;
	  st2:
	      if(count == 5'b00101) // 5    
          next_state = st3;           
        else                          
          next_state = st2;         
    st3:                             
        if(count == 5'b00110) // 6 
          next_state = st4;        
        else                       
          next_state = st3; 
    st4:                                  
        if(count == 5'b00111) // 7 
          next_state = st5;        
        else                       
          next_state = st4;
    st5:                                   
        if(count == 5'b01000) // 8
          next_state = st6;        
        else                       
          next_state = st5;   
    st6:                                
        if(count == 5'b01001) // 9 
          next_state = st7;        
        else                       
          next_state = st6; 
    st7:                                  
        if(count == 5'b01010) // 10 
          next_state = st8;        
        else                       
          next_state = st7; 
    st8:                                  
        if(count == 5'b01011) // 11 
          next_state = st9;        
        else                       
          next_state = st8; 
    st9:                                  
        if(count == 5'b01100) // 12 
          next_state = st10;        
        else                       
          next_state = st9; 
    st10:
        if(count == 5'b10111)   // 21                                    
//        if(count == 5'b10110) // 22       
          next_state = idle;              
        else                             
          next_state = st10;                                          
    default :
          next_state = idle;
  endcase
end
//
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	  lcd_data <= #DLY 8'b0000_0000; //00
	else if(current_state == st1)   
	  lcd_data <= #DLY 8'b0000_0001; //01
	else if(current_state == st2)
	  lcd_data <= #DLY 8'b0000_0010; //02
	else if(current_state == st3)
	  lcd_data <= #DLY 8'b0000_0110; //06
	else if(current_state == st4)    
	  lcd_data <= #DLY 8'b0000_1111; //0F
	else if(current_state == st5)   
	  lcd_data <= #DLY 8'b0001_1000; //18
	else if(current_state == st6)   
	  lcd_data <= #DLY 8'b0011_1000; //38
	else if(current_state == st7)
	  lcd_data <= #DLY 8'b0100_0000; //40
	else if(current_state == st8)
	  lcd_data <= #DLY 8'b1000_0000; //80
	else if(current_state == st9)
	  lcd_data <= #DLY 8'b0000_0000; //00
/*-----------------------------------
	else if((current_state == st10)&(count == 5'b01100))//12
	  lcd_data <= #DLY 8'b0101_0000; // P	  
	else if((current_state == st10)&(count == 5'b01101))//13
	  lcd_data <= #DLY 8'b0100_0001; // A
	  */
//-----------------------------------------------------------------------	  
	else if((current_state == st10)&(count == 5'b01110))//14
	  lcd_data <= #DLY 8'b0101_0000; //50 P	  
	else if((current_state == st10)&(count == 5'b01111))//15
	  lcd_data <= #DLY 8'b0100_0001; //41 A
	else if((current_state == st10)&(count == 5'b10000))//16
	  lcd_data <= #DLY 8'b0100_1110; //4E N   
	else if((current_state == st10)&(count == 5'b10001))//17
	  lcd_data <= #DLY 8'b0101_0111; //57 W
	else if((current_state == st10)&(count == 5'b10010))//18  
	  lcd_data <= #DLY 8'b0100_0101; //45 E 
	else if((current_state == st10)&(count == 5'b10011))//19
	  lcd_data <= #DLY 8'b0100_1110; //4E N
	else if((current_state == st10)&(count == 5'b10100))//20
	  lcd_data <= #DLY 8'b0101_0010; //52 R         
	else if((current_state == st10)&(count == 5'b10101))//21 
	  lcd_data <= #DLY 8'b0100_1111; //4F O 
  else if((current_state == st10)&(count == 5'b10110))//22
	  lcd_data <= #DLY 8'b0100_1110; //4E N
	else if((current_state == st10)&(count == 5'b10111))//23  
	  lcd_data <= #DLY 8'b0100_0111; //47 G    
//--------------------------------------------------------------------------	  
	else
	  lcd_data <= #DLY 8'b0000_0000;	  
end                       

always @(posedge clk or negedge rst_n)
//always @(rst_n or current_state)
begin
	if(!rst_n)
	  lcd_rs <= #DLY 1'b0;
	else if(current_state == st10)
	  lcd_rs <= #DLY 1'b1;
	else
	  lcd_rs <= #DLY 1'b0;
end    

always @(posedge clk or negedge rst_n)  
//always @(rst_n or current_state)
begin                                   
	if(!rst_n)                            
	  lcd_rw <= #DLY 1'b0;                
	else if(current_state == st9)        
	  lcd_rw <= #DLY 1'b1;                
	else                                  
	  lcd_rw <= #DLY 1'b0;                
end                                  

endmodule