test.v

FPGA驱动STN （16x2）的程序

/*============================================================================
                         clock and reset product module
=============================================================================*/
`timescale 1ns / 100ps
module test(
            clk_in,
            rst_n
);                 
output      clk_in;
output      rst_n;
            
reg         clk_in;
reg         rst_n;
                   
parameter          clk_in_PERIOD = 20;         //default time cycle
parameter          MULT_RATIO = 10;         //default reset time multiplier
parameter          RESET_TIME = MULT_RATIO * clk_in_PERIOD + 1;

wire               lcd_e;   
wire               lcd_rs;  
wire               lcd_rw;  
wire [7:0]         lcd_data; 
/*--------------------------------------main code-------------------------------*/
initial
begin
                   rst_n = 1'b0;
  #RESET_TIME      rst_n = 1'b1;
end                
                   
initial            
begin              
                   clk_in = 1'b0;
  forever     
  #(clk_in_PERIOD/2)  clk_in <= ~clk_in;              
end
/*----------------------------------
top U_top(              
          // input port 
          .clk_in(clk_in),    
          .rst_n(rst_n),        
          // out port   
          .lcd_e(lcd_e),        
          .lcd_rs(lcd_rs),       
          .lcd_rw(lcd_rw),       
          .lcd_data(lcd_data)      
);                               
//----------------------------------*/
lcd_control u_lcd(                  
                  .clk(clk_in),         
                  .rst_n(rst_n),           
                              
                  .lcd_e(lcd_e),           
                  .lcd_rs(lcd_rs),         
                  .lcd_rw(lcd_rw),         
                  .lcd_data(lcd_data)                              
);                                   



endmodule