test_clk.v

来自「FPGA驱动STN （16x2）的程序」· Verilog 代码 · 共 40 行

`timescale 1ns / 100ps
module test_clk(
                clk_in,
                rst_n
);                 
output          clk_in;
output          rst_n;
                
reg             clk_in;
reg             rst_n;
                
parameter       clk_in_PERIOD = 20;         //default time cycle
parameter       MULT_RATIO = 10;         //default reset time multiplier
parameter       RESET_TIME = MULT_RATIO * clk_in_PERIOD + 1;

wire            clk_out;
//--------------------------------------
initial                                            
begin                                              
                   rst_n = 1'b0;                   
  #RESET_TIME      rst_n = 1'b1;                   
end                                                
                                                   
initial                                            
begin                                              
                   clk_in = 1'b0;                  
  forever                                          
  #(clk_in_PERIOD/2)  clk_in <= ~clk_in;           
end                                                

//--------------------------------------
clk_div U_clkdiv(                  
                 //input port      
                 .clk_in(clk_in), // 50Mhz  
                 .rst_n(rst_n),            
                 //output port     
                 .clk_out(clk_out) // 1s     
);         

endmodule