gd00_nand_boot.s

对nand flash的读写

	AREA	BOOT, CODE, READONLY
	ENTRY

;vector table
	b RESET
	b DEAD_LOOP				;UNDEF_INS
	b DEAD_LOOP				;UNDEF_INS
	b DEAD_LOOP				;UNDEF_INS
	b DEAD_LOOP				;UNDEF_INS
	b DEAD_LOOP				;UNDEF_INS
	b DEAD_LOOP				;UNDEF_INS

RESET

;配置工作频率为60MHz
	
	ldr		r1, =0x1000100c
	ldr		r2, =0x17fff
	str		r2,[r1]
	        	
	ldr		r1, =0x10001014
	ldr		r2, =0x1
	str		r2,[r1]
	        	
	ldr		r1, =0x10001000
	ldr		r2, =0x018000cd
	str		r2,[r1]
	        	
	ldr		r1, =0x10001004
	ldr		r2, =0X230
	str		r2,[r1]
	        	
	ldr		r1, =0x10001004
	ldr		r2, =0X1230
	str		r2,[r1]
	
	
	
	;;real config now	
	ldr		 r0, =0xffffffff        ; DMA interrupt complete clear
	ldr		 r1, =0x10001090		; DMA interrupt error clear
	ldr		 r2, =0x10001060		; 
	ldr 	 r3, =0x10000008		; interrupt mask register
	ldr		 r4, =0x1000100c		; PMU open all module
	str 	 r0, [r1]
	str		 r0, [r2]
	str 	 r0, [r3]				; mask all the interrupts
	str 	 r0, [r4]				; enable all module
	mov 	 r0, #0x0
	str 	 r0, [r1]
	str		 r0, [r2]	
	
	;;config nand and EMI
	ldr		 r0, =0x11000118
	ldr  	 r1, =0x02200aaa 
	str 	 r1, [r0]				; NAND configure register
	
	ldr		r1, =0x11000014			
    ldr		r2, =0x00004077		    ; configure SMCONF1
    str		r2, [ r1 ]
   	ldr		r1, =0x11000018         ; configure SMCONF2
    ldr		r2, =0x80000500
    str		r2, [ r1 ]
    
    
	ldr r0, = 0x11001000 			; DMA channel 0 base address
	add r1, r0, #0x4   				; dest register relative address
	add r2, r0, #0xc				; control register relative address
	add r3, r0, #0x10				; configure register relative address
	ldr r4, =0x1b00					; number of pages to be transmitted 
	ldr r5, = 0x0020249b			; DMA control reg parameters
	ldr r6, = 0x0000031d			; DMA configure reg parameters
	ldr r7, = 0x11000200 			; nand flash fifo address, src
	ldr r10, = 0x80000000
	
	ldr r11, = 0x2000				; nand internal source address
	ldr r8, = 0x30002000			; destination address in Sdram
	

	
LOOP
	mov r9, r11, lsr #1
	ldr r12, = 0x11000100
	str r9, [r12]					; update NAND internal address
	
	str r7, [r0]					; src address
	str r8, [r1]					; dest address
	str r5, [r2]					; control register
	str r6, [r3]					; configure register
	
	ldr r12, = (0x11000100 +0x04)	; Nand flash command register 
	str r10, [r12];					; read command 

	mov r12, #0x800					; must wait some time  (wuer) 
NOPWAIT	
	subs r12, r12, #0x1
	cmp r12, #0      			
	bne NOPWAIT
	
	ldr r12, = (0x11000100 +0x24) 	; Nand Idle register  
WAIT
	ldr r13, [r12]					; read nand flash idle register
	and r13, r13, #0x01
	cmp r13, #0x01
	bne WAIT						; Not idle yet, keep waiting
				
	add r11, r11, #0x200	
	add r8, r8, #0x200				; page adress update
		
	subs r4, r4, #1				
	cmp r4, #0  								 				
	bne LOOP						; Not complete the action yet, then continue





	;;move 512 bytes from 0x1fff0000 to 0x30000000
	ldr r0, =0x0				
	ldr r1, =0x30000000				; move dest address to Sdram
	mov r2, #0x200					; size of code to be moved(in byte)
MOVE
	ldrb r3, [r0]
	strb r3, [r1]
	sub	 r2, r2, #1
	add r0, r0, #1
	add r1, r1, #1
	cmp r2, #0x0					; complete?
	bne MOVE						; Not yet, then continue
	
	
	;;remap SDRAM to address 0x0
Remap
	ldr r1, =0x11000010
	mov r2, #0x0b
	str r2, [r1]					; remap step1
	
	ldr r1, =0x1100001c
	mov r2, #0x1
	str r2, [r1]					; remap step2,then remap action OK
	
	ldr pc,=0x30002000				; no return, JUMP to kernel initialization 
									; turning to OS world NOW!
	


  
DEAD_LOOP
	b DEAD_LOOP	


    END