hardware.h

对nand flash的读写

#ifndef _HARDWARE_H
#define _HARDWARE_H

#include 	"hardware_reg.h"

//***************************************
//PMU module clk
//*************************************
#define	CLK_INTC	(1 << 14)
#define	CLK_PMU		(1 << 13)
#define	CLK_RTC		(1 << 12)
#define	CLK_GPT		(1 << 11)
#define	CLK_SPI		(1 << 10)
#define	CLK_UART0	(1 << 9)
#define	CLK_UART1	(1 << 8)
#define	CLK_GPIO	(1 << 7)
#define	CLK_MMC		(1 << 6)
#define	CLK_AC97	(1 << 5)
#define	CLK_DMA		(1 << 4)
#define	CLK_MMA		(1 << 3)
#define	CLK_LCDC	(1 << 2)
#define	CLK_ESRAM	(1 << 1)
#define	CLK_EMI		(1)


/*************************************
	macros for INTC
*************************************/

/*interrupt resources */


#define		INT_RTC					31		
#define		INT_DMA					30	
#define		INT_EMI					29
#define		INT_GPT					28
#define		INT_USB					27
#define		INT_SPI					26
#define 	INT_MMC					25
#define		INT_UART1				24
#define		INT_UART2				23
#define		INT_I2C					22
#define		INT_AC97				21
#define		INT_MMA					20	
#define		INT_EXT17				19	
#define		INT_EXT16				18
#define		INT_EXT15				17	
//#define		INT_NONE				16			
#define		INT_EXT0				15
#define		INT_EXT1				1				
#define		INT_EXT2				13
#define		INT_EXT3				12
#define		INT_EXT4				11
#define		INT_EXT5				10
#define		INT_EXT6				9
#define		INT_EXT7				8
#define		INT_EXT8				7
#define		INT_EXT9				6
#define		INT_EXT10				5
#define		INT_EXT11				4
#define		INT_EXT12				3
#define		INT_EXT13				2
#define		INT_EXT14				14






/*****************************************
	macros for EMI
*****************************************/


#define	EMIADDR_CSGBAB_val		0x24002000          		//base adress of csa:0x20000000
                                                            //base adress of csb:0x24000000(none now)
													 
#define	EMIADDR_CSGBCD_val		0x2c002800     		    	//base adress of csc:0x28000000
       					                					//base adress of csc:0x2C000000(none now)   
       					                	
#define	EMIADDR_CSGBEF_val		0x34003000    				//base adress of csc:0x30000000
                                                            //base adress of csc:0x34000000 

#define	EMIADDR_SMCONF_val	   	0x9b010388  	 			//write cycle: 3     read cycle:3
															//csa:32_bit sram
															//csb:none
															//csc:32_bit sram
															//csd:none
															//cde:16_bit sdram
															//cdf:32 bit sdram


#define EMIADDR_SDCONF1_val		0x0110a077			//12 row * 9 column
													//non_Interleaved Address Mode
													//2 row every flesh clock edge
													//hang_up after 64 clocks after last access
													//CAS = 2 clock
													//3 clock between precharge and active command
													//4 clock between active and write/read command toward the same bank
													//7 clock between refresh command and later commands
									
#define EMIADDR_SDCONF2_val		0x80001860			//Initialize sdam;
													//refresh cyccle:64*0x186 clocks
													//refresh all rows once a time


#define EMIADDR_NANDCONF_VAL    0x02200aaa          //4 address 0x1aa3aa      
                                                    //Trr 10 cycles
                                                    //Tclh 2 cycles
                                                    //Talh 2 cycles
                                                    //Twh  3 cycles
                                                    //Read_width 10 cycles
                                                    //Writ_width 10 cycles
                                                                                                       
                                                    
/*****************************************
	macros for nand command
*****************************************/  
#define NAND_CMD_READ0			0x80000000                                     //highesn bit means enable in GIII controller
#define NAND_CMD_READ1			1
#define NAND_CMD_PAGEPROG		0x10
#define NAND_CMD_READOOB		0x50
#define NAND_CMD_ERASE1			0x80000060
#define NAND_CMD_STATUS			0x80000070
#define NAND_CMD_SEQIN			0x80000080
#define NAND_CMD_READID			0x90
#define NAND_CMD_ERASE2			0xd0
#define NAND_CMD_RESET			0x800000ff                                        
                                                    

                                        
                                                    
/****************************************
	functions for all modules
****************************************/


/*EMI*/ 
#define YES 1
#define NO 0


int nand_rd_page(U32 page, U32*buffer,  U32 do_read);
int nand_read_page_com (U32 page,  U32 *buf);
int nand_write_page_com (U32 page, U32 *buf);
int nand_erase_block(U32 blockhead);
void init_nand(void);
void int_serv_emi(void);






/****************************************
	macros  for write and read registers
****************************************/
#define write_reg(reg, data) \
	*(RP)reg = data

#define read_reg(reg) \
	*(RP)reg

/****************************************
	for print function
****************************************/

extern ER print( U32 addr, U32 errsymb );
extern ER print_num( U32 addr, U32 num );
extern ER prints(char *s);


#endif