fsm.tan.rpt

有限状态机的设计，包括仿真文件以及sof文件

+---------------------------------------------------------------------+
; tsu                                                                 ;
+-------+--------------+------------+------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To            ; To Clock ;
+-------+--------------+------------+------+---------------+----------+
; N/A   ; None         ; 2.603 ns   ; In   ; State[0]~reg0 ; Clk      ;
; N/A   ; None         ; 2.599 ns   ; In   ; State[2]~reg0 ; Clk      ;
; N/A   ; None         ; 2.595 ns   ; In   ; State[1]~reg0 ; Clk      ;
+-------+--------------+------------+------+---------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To       ; From Clock ;
+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 14.720 ns  ; Q~reg0        ; Q        ; Clk        ;
; N/A   ; None         ; 11.281 ns  ; State[2]~reg0 ; State[2] ; Clk        ;
; N/A   ; None         ; 11.278 ns  ; State[1]~reg0 ; State[1] ; Clk        ;
; N/A   ; None         ; 11.278 ns  ; State[0]~reg0 ; State[0] ; Clk        ;
+-------+--------------+------------+---------------+----------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To            ; To Clock ;
+---------------+-------------+-----------+------+---------------+----------+
; N/A           ; None        ; -2.543 ns ; In   ; State[1]~reg0 ; Clk      ;
; N/A           ; None        ; -2.547 ns ; In   ; State[2]~reg0 ; Clk      ;
; N/A           ; None        ; -2.551 ns ; In   ; State[0]~reg0 ; Clk      ;
+---------------+-------------+-----------+------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Aug 28 21:22:15 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FSM -c FSM --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk" is an undefined clock
Info: Clock "Clk" Internal fmax is restricted to 275.03 MHz between source register "State[0]~reg0" and destination register "Q~reg0"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.303 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N7; Fanout = 5; REG Node = 'State[0]~reg0'
            Info: 2: + IC(0.565 ns) + CELL(0.738 ns) = 1.303 ns; Loc. = LC_X34_Y16_N9; Fanout = 2; REG Node = 'Q~reg0'
            Info: Total cell delay = 0.738 ns ( 56.64 % )
            Info: Total interconnect delay = 0.565 ns ( 43.36 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "Clk" to destination register is 7.789 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'
                Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N9; Fanout = 2; REG Node = 'Q~reg0'
                Info: Total cell delay = 2.180 ns ( 27.99 % )
                Info: Total interconnect delay = 5.609 ns ( 72.01 % )
            Info: - Longest clock path from clock "Clk" to source register is 7.789 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'
                Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N7; Fanout = 5; REG Node = 'State[0]~reg0'
                Info: Total cell delay = 2.180 ns ( 27.99 % )
                Info: Total interconnect delay = 5.609 ns ( 72.01 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "State[0]~reg0" (data pin = "In", clock pin = "Clk") is 2.603 ns
    Info: + Longest pin to register delay is 10.355 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 3; PIN Node = 'In'
        Info: 2: + IC(8.148 ns) + CELL(0.738 ns) = 10.355 ns; Loc. = LC_X34_Y16_N7; Fanout = 5; REG Node = 'State[0]~reg0'
        Info: Total cell delay = 2.207 ns ( 21.31 % )
        Info: Total interconnect delay = 8.148 ns ( 78.69 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "Clk" to destination register is 7.789 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'
        Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N7; Fanout = 5; REG Node = 'State[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 27.99 % )
        Info: Total interconnect delay = 5.609 ns ( 72.01 % )
Info: tco from clock "Clk" to destination pin "Q" through register "Q~reg0" is 14.720 ns
    Info: + Longest clock path from clock "Clk" to source register is 7.789 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'
        Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N9; Fanout = 2; REG Node = 'Q~reg0'
        Info: Total cell delay = 2.180 ns ( 27.99 % )
        Info: Total interconnect delay = 5.609 ns ( 72.01 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.707 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N9; Fanout = 2; REG Node = 'Q~reg0'
        Info: 2: + IC(4.583 ns) + CELL(2.124 ns) = 6.707 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'Q'
        Info: Total cell delay = 2.124 ns ( 31.67 % )
        Info: Total interconnect delay = 4.583 ns ( 68.33 % )
Info: th for register "State[1]~reg0" (data pin = "In", clock pin = "Clk") is -2.543 ns
    Info: + Longest clock path from clock "Clk" to destination register is 7.789 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'
        Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N0; Fanout = 5; REG Node = 'State[1]~reg0'
        Info: Total cell delay = 2.180 ns ( 27.99 % )
        Info: Total interconnect delay = 5.609 ns ( 72.01 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 10.347 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 3; PIN Node = 'In'
        Info: 2: + IC(8.140 ns) + CELL(0.738 ns) = 10.347 ns; Loc. = LC_X34_Y16_N0; Fanout = 5; REG Node = 'State[1]~reg0'
        Info: Total cell delay = 2.207 ns ( 21.33 % )
        Info: Total interconnect delay = 8.140 ns ( 78.67 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Tue Aug 28 21:22:17 2007
    Info: Elapsed time: 00:00:02