fsm.tan.rpt

有限状态机的设计，包括仿真文件以及sof文件

Classic Timing Analyzer report for FSM
Tue Aug 28 21:22:17 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'Clk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                      ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From          ; To            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 2.603 ns                                       ; In            ; State[0]~reg0 ; --         ; Clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 14.720 ns                                      ; Q~reg0        ; Q             ; Clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -2.543 ns                                      ; In            ; State[1]~reg0 ; --         ; Clk      ; 0            ;
; Clock Setup: 'Clk'           ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0]~reg0 ; Q~reg0        ; Clk        ; Clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;               ;               ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clk'                                                                                                                                                                                 ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From          ; To            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0]~reg0 ; Q~reg0        ; Clk        ; Clk      ; None                        ; None                      ; 1.303 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[2]~reg0 ; State[0]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 1.167 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[2]~reg0 ; Q~reg0        ; Clk        ; Clk      ; None                        ; None                      ; 1.166 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[2]~reg0 ; State[1]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 1.165 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[2]~reg0 ; State[2]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 1.165 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0]~reg0 ; State[1]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 1.061 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0]~reg0 ; State[2]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 1.059 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0]~reg0 ; State[0]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 1.054 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q~reg0        ; Q~reg0        ; Clk        ; Clk      ; None                        ; None                      ; 1.036 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1]~reg0 ; State[0]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 0.913 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1]~reg0 ; Q~reg0        ; Clk        ; Clk      ; None                        ; None                      ; 0.911 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1]~reg0 ; State[2]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 0.908 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1]~reg0 ; State[1]~reg0 ; Clk        ; Clk      ; None                        ; None                      ; 0.900 ns                ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+