fsm.v

来自「有限状态机的设计，包括仿真文件以及sof文件」· Verilog 代码 · 共 65 行

module FSM( In, Clk, Reset, State, Q  );

input In,Clk,Reset;
output Q;
output [3:0] State;

reg Q;
reg [3:0] State;

parameter A = 4'b1010,
          B = 4'b1011,
          C = 4'b1100,
          D = 4'b1101,
          E = 4'b1110,
          F = 4'b1111;

always @( posedge Clk or posedge Reset )
if (Reset) begin
	State <= A;
	Q   <= 1'b0;
end
else
	case (State)
		A:	begin                //A=0
				Q <= 1'b0;
				if(In) 
					State <= B;
			end
		B:	begin               //B=1
				Q <= 1'b0;
				if(~In) 
					State <= C;
			end
		C:	begin               //C=10
				Q <= 1'b0;
				if(~In) 
					State <= D;
				else
					State <= B;
			end
		D:	begin               //D=100
				Q <=1'b0;
				if(In) 
					State <= E;
				else 
					State <= A;
			end
		E:	begin               //E=1001 
				Q <= 1'b0;
				if(In)         
					State <= F;
				else 
					State <= C;
			end
		F:	begin            //F=10011  
				Q <= 1'b1;
				if(In) 
					State <= B;
				else 
					State <= C;
			end
		default: State <= A;
	endcase

endmodule