fsm.tan.qmsg

有限状态机的设计，包括仿真文件以及sof文件

{ "Info" "ITDB_TSU_RESULT" "State\[0\]~reg0 In Clk 2.603 ns register " "Info: tsu for register \"State\[0\]~reg0\" (data pin = \"In\", clock pin = \"Clk\") is 2.603 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.355 ns + Longest pin register " "Info: + Longest pin to register delay is 10.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns In 1 PIN PIN_1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 3; PIN Node = 'In'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { In } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.148 ns) + CELL(0.738 ns) 10.355 ns State\[0\]~reg0 2 REG LC_X34_Y16_N7 5 " "Info: 2: + IC(8.148 ns) + CELL(0.738 ns) = 10.355 ns; Loc. = LC_X34_Y16_N7; Fanout = 5; REG Node = 'State\[0\]~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.886 ns" { In State[0]~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 21.31 % ) " "Info: Total cell delay = 2.207 ns ( 21.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.148 ns ( 78.69 % ) " "Info: Total interconnect delay = 8.148 ns ( 78.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "10.355 ns" { In State[0]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "10.355 ns" { In In~out0 State[0]~reg0 } { 0.000ns 0.000ns 8.148ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 7.789 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk\" to destination register is 7.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.609 ns) + CELL(0.711 ns) 7.789 ns State\[0\]~reg0 2 REG LC_X34_Y16_N7 5 " "Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N7; Fanout = 5; REG Node = 'State\[0\]~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.320 ns" { Clk State[0]~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 27.99 % ) " "Info: Total cell delay = 2.180 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.609 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.609 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk State[0]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 State[0]~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "10.355 ns" { In State[0]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "10.355 ns" { In In~out0 State[0]~reg0 } { 0.000ns 0.000ns 8.148ns } { 0.000ns 1.469ns 0.738ns } "" } } { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk State[0]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 State[0]~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Q Q~reg0 14.720 ns register " "Info: tco from clock \"Clk\" to destination pin \"Q\" through register \"Q~reg0\" is 14.720 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 7.789 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 7.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.609 ns) + CELL(0.711 ns) 7.789 ns Q~reg0 2 REG LC_X34_Y16_N9 2 " "Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N9; Fanout = 2; REG Node = 'Q~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.320 ns" { Clk Q~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 27.99 % ) " "Info: Total cell delay = 2.180 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.609 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.609 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk Q~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 Q~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.707 ns + Longest register pin " "Info: + Longest register to pin delay is 6.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q~reg0 1 REG LC_X34_Y16_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N9; Fanout = 2; REG Node = 'Q~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.583 ns) + CELL(2.124 ns) 6.707 ns Q 2 PIN PIN_3 0 " "Info: 2: + IC(4.583 ns) + CELL(2.124 ns) = 6.707 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'Q'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { Q~reg0 Q } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 31.67 % ) " "Info: Total cell delay = 2.124 ns ( 31.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.583 ns ( 68.33 % ) " "Info: Total interconnect delay = 4.583 ns ( 68.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { Q~reg0 Q } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "6.707 ns" { Q~reg0 Q } { 0.000ns 4.583ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk Q~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 Q~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { Q~reg0 Q } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "6.707 ns" { Q~reg0 Q } { 0.000ns 4.583ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "State\[1\]~reg0 In Clk -2.543 ns register " "Info: th for register \"State\[1\]~reg0\" (data pin = \"In\", clock pin = \"Clk\") is -2.543 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 7.789 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to destination register is 7.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.609 ns) + CELL(0.711 ns) 7.789 ns State\[1\]~reg0 2 REG LC_X34_Y16_N0 5 " "Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N0; Fanout = 5; REG Node = 'State\[1\]~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.320 ns" { Clk State[1]~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 27.99 % ) " "Info: Total cell delay = 2.180 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.609 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.609 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk State[1]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 State[1]~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.347 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.347 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns In 1 PIN PIN_1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 3; PIN Node = 'In'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { In } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.140 ns) + CELL(0.738 ns) 10.347 ns State\[1\]~reg0 2 REG LC_X34_Y16_N0 5 " "Info: 2: + IC(8.140 ns) + CELL(0.738 ns) = 10.347 ns; Loc. = LC_X34_Y16_N0; Fanout = 5; REG Node = 'State\[1\]~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.878 ns" { In State[1]~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 21.33 % ) " "Info: Total cell delay = 2.207 ns ( 21.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.140 ns ( 78.67 % ) " "Info: Total interconnect delay = 8.140 ns ( 78.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "10.347 ns" { In State[1]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "10.347 ns" { In In~out0 State[1]~reg0 } { 0.000ns 0.000ns 8.140ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk State[1]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 State[1]~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "10.347 ns" { In State[1]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "10.347 ns" { In In~out0 State[1]~reg0 } { 0.000ns 0.000ns 8.140ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 28 21:22:17 2007 " "Info: Processing ended: Tue Aug 28 21:22:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}