fsm.tan.qmsg

有限状态机的设计，包括仿真文件以及sof文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 28 21:22:15 2007 " "Info: Processing started: Tue Aug 28 21:22:15 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off FSM -c FSM --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FSM -c FSM --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" {  } { { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 3 -1 0 } } { "e:/program files/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "Clk register register State\[0\]~reg0 Q~reg0 275.03 MHz Internal " "Info: Clock \"Clk\" Internal fmax is restricted to 275.03 MHz between source register \"State\[0\]~reg0\" and destination register \"Q~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.303 ns + Longest register register " "Info: + Longest register to register delay is 1.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns State\[0\]~reg0 1 REG LC_X34_Y16_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N7; Fanout = 5; REG Node = 'State\[0\]~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { State[0]~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.738 ns) 1.303 ns Q~reg0 2 REG LC_X34_Y16_N9 2 " "Info: 2: + IC(0.565 ns) + CELL(0.738 ns) = 1.303 ns; Loc. = LC_X34_Y16_N9; Fanout = 2; REG Node = 'Q~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { State[0]~reg0 Q~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 56.64 % ) " "Info: Total cell delay = 0.738 ns ( 56.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.565 ns ( 43.36 % ) " "Info: Total interconnect delay = 0.565 ns ( 43.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { State[0]~reg0 Q~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "1.303 ns" { State[0]~reg0 Q~reg0 } { 0.000ns 0.565ns } { 0.000ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 7.789 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 7.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.609 ns) + CELL(0.711 ns) 7.789 ns Q~reg0 2 REG LC_X34_Y16_N9 2 " "Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N9; Fanout = 2; REG Node = 'Q~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.320 ns" { Clk Q~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 27.99 % ) " "Info: Total cell delay = 2.180 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.609 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.609 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk Q~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 Q~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 7.789 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 7.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'Clk'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.609 ns) + CELL(0.711 ns) 7.789 ns State\[0\]~reg0 2 REG LC_X34_Y16_N7 5 " "Info: 2: + IC(5.609 ns) + CELL(0.711 ns) = 7.789 ns; Loc. = LC_X34_Y16_N7; Fanout = 5; REG Node = 'State\[0\]~reg0'" {  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.320 ns" { Clk State[0]~reg0 } "NODE_NAME" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 27.99 % ) " "Info: Total cell delay = 2.180 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.609 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.609 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk State[0]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 State[0]~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk Q~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 Q~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk State[0]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 State[0]~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { State[0]~reg0 Q~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "1.303 ns" { State[0]~reg0 Q~reg0 } { 0.000ns 0.565ns } { 0.000ns 0.738ns } "" } } { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk Q~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 Q~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.789 ns" { Clk State[0]~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "7.789 ns" { Clk Clk~out0 State[0]~reg0 } { 0.000ns 0.000ns 5.609ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q~reg0 } "NODE_NAME" } } { "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/61/quartus/bin/Technology_Viewer.qrui" "" { Q~reg0 } {  } {  } "" } } { "FSM.v" "" { Text "F:/quartus/FPGA3/FSM.v" 23 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}