fsm.map.rpt

有限状态机的设计，包括仿真文件以及sof文件

+----------------------------------+-----------------+------------------------+------------------------------+


+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+---------------------------------------------+---------------+
; Resource                                    ; Usage         ;
+---------------------------------------------+---------------+
; Total logic elements                        ; 6             ;
;     -- Combinational with no register       ; 2             ;
;     -- Register only                        ; 0             ;
;     -- Combinational with a register        ; 4             ;
;                                             ;               ;
; Logic element usage by number of LUT inputs ;               ;
;     -- 4 input functions                    ; 4             ;
;     -- 3 input functions                    ; 0             ;
;     -- 2 input functions                    ; 0             ;
;     -- 1 input functions                    ; 1             ;
;     -- 0 input functions                    ; 1             ;
;                                             ;               ;
; Logic elements by mode                      ;               ;
;     -- normal mode                          ; 6             ;
;     -- arithmetic mode                      ; 0             ;
;     -- qfbk mode                            ; 0             ;
;     -- register cascade mode                ; 0             ;
;     -- synchronous clear/load mode          ; 0             ;
;     -- asynchronous clear/load mode         ; 4             ;
;                                             ;               ;
; Total registers                             ; 4             ;
; I/O pins                                    ; 0             ;
; Maximum fan-out node                        ; State[0]~reg0 ;
; Maximum fan-out                             ; 5             ;
; Total fan-out                               ; 30            ;
; Average fan-out                             ; 2.14          ;
+---------------------------------------------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |FSM                       ; 6 (6)       ; 4            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |FSM                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; State[3]~reg0                         ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 1 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; State[1]~reg0                          ; 5       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |FSM ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; A              ; 1010  ; Unsigned Binary                            ;
; B              ; 1011  ; Unsigned Binary                            ;
; C              ; 1100  ; Unsigned Binary                            ;
; D              ; 1101  ; Unsigned Binary                            ;
; E              ; 1110  ; Unsigned Binary                            ;
; F              ; 1111  ; Unsigned Binary                            ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Aug 28 21:21:58 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FSM -c FSM
Info: Found 1 design units, including 1 entities, in source file FSM.v
    Info: Found entity 1: FSM
Info: Elaborating entity "FSM" for the top level hierarchy
Info: Power-up level of register "State[3]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "State[3]~reg0" with stuck data_in port to stuck value VCC
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "State[3]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 14 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 5 output pins
    Info: Implemented 6 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 126 megabytes of memory during processing
    Info: Processing ended: Tue Aug 28 21:22:00 2007
    Info: Elapsed time: 00:00:02