ledtest.rpt

CPLD本科教育的实体实例

  57   (88)  (F)      INPUT               0      0   0    0    0    1    0  d


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               e:\cpld\ledtest.rpt
ledtest

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  63     97    G     OUTPUT      t        0      0   0    1    0    0    0  a0
  65    101    G     OUTPUT      t        0      0   0    1    0    0    0  b0
  68    105    G     OUTPUT      t        0      0   0    1    0    0    0  c0
  70    109    G     OUTPUT      t        0      0   0    1    0    0    0  d0


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               e:\cpld\ledtest.rpt
ledtest

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                 Logic cells placed in LAB 'G'
        +------- LC97 a0
        | +----- LC101 b0
        | | +--- LC105 c0
        | | | +- LC109 d0
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'G'
LC      | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':

Pin
41   -> * - - - | - - - - - - * - | <-- a
60   -> - * - - | - - - - - - * - | <-- b
58   -> - - * - | - - - - - - * - | <-- c
57   -> - - - * | - - - - - - * - | <-- d


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\cpld\ledtest.rpt
ledtest

** EQUATIONS **

a        : INPUT;
b        : INPUT;
c        : INPUT;
d        : INPUT;

-- Node name is 'a0' 
-- Equation name is 'a0', location is LC097, type is output.
 a0      = LCELL(!a $  GND);

-- Node name is 'b0' 
-- Equation name is 'b0', location is LC101, type is output.
 b0      = LCELL(!b $  GND);

-- Node name is 'c0' 
-- Equation name is 'c0', location is LC105, type is output.
 c0      = LCELL(!c $  GND);

-- Node name is 'd0' 
-- Equation name is 'd0', location is LC109, type is output.
 d0      = LCELL(!d $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\cpld\ledtest.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,765K