test.map.rpt

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

Analysis & Synthesis report for test
Wed Nov 07 11:04:41 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Parameter Settings for User Entity Instance: initial_block:inst9|get_response:inst3
 13. Parameter Settings for User Entity Instance: initial_block:inst9|send_cmd:inst4
 14. Parameter Settings for User Entity Instance: initial_block:inst9|shift_r1:inst5
 15. Parameter Settings for User Entity Instance: initial_block:inst9|shift_reg:inst7
 16. Parameter Settings for User Entity Instance: sd_control:inst
 17. Parameter Settings for User Entity Instance: sd_control:inst|shift_reg:cmd18
 18. Parameter Settings for User Entity Instance: fifo_control:inst26
 19. Parameter Settings for User Entity Instance: mux_2bus:inst10|lpm_mux:lpm_mux_component
 20. Parameter Settings for User Entity Instance: ram_4_32:inst24|altsyncram:altsyncram_component
 21. Parameter Settings for User Entity Instance: ram_4_32:inst1|altsyncram:altsyncram_component
 22. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 23. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 24. SignalTap II Logic Analyzer Settings
 25. Analysis & Synthesis Equations
 26. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Wed Nov 07 11:04:41 2007    ;
; Quartus II Version                 ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name                      ; test                                     ;
; Top-level Entity Name              ; test                                     ;
; Family                             ; Cyclone II                               ;
; Total combinational functions      ; 1795                                     ;