test.map.eqn

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

WB2_q_b[3]_PORT_B_data_out = MEMORY(WB2_q_b[3]_PORT_A_data_in_reg, , WB2_q_b[3]_PORT_A_address_reg, WB2_q_b[3]_PORT_B_address_reg, WB2_q_b[3]_PORT_A_write_enable_reg, WB2_q_b[3]_PORT_B_read_enable_reg, , , WB2_q_b[3]_clock_0, WB2_q_b[3]_clock_1, WB2_q_b[3]_clock_enable_0, WB2_q_b[3]_clock_enable_1, , );
WB2_q_b[3]_PORT_B_data_out_reg = DFFE(WB2_q_b[3]_PORT_B_data_out, WB2_q_b[3]_clock_1, , , WB2_q_b[3]_clock_enable_1);
WB2_q_b[23] = WB2_q_b[3]_PORT_B_data_out_reg[5];

--WB2_q_b[27] is ram_4_32:inst24|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[27]
WB2_q_b[3]_PORT_A_data_in = sd2_dat[3];
WB2_q_b[3]_PORT_A_data_in_reg = DFFE(WB2_q_b[3]_PORT_A_data_in, WB2_q_b[3]_clock_0, , , WB2_q_b[3]_clock_enable_0);
WB2_q_b[3]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB2_q_b[3]_PORT_A_address_reg = DFFE(WB2_q_b[3]_PORT_A_address, WB2_q_b[3]_clock_0, , , WB2_q_b[3]_clock_enable_0);
WB2_q_b[3]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB2_q_b[3]_PORT_B_address_reg = DFFE(WB2_q_b[3]_PORT_B_address, WB2_q_b[3]_clock_1, , , WB2_q_b[3]_clock_enable_1);
WB2_q_b[3]_PORT_A_write_enable = VCC;
WB2_q_b[3]_PORT_A_write_enable_reg = DFFE(WB2_q_b[3]_PORT_A_write_enable, WB2_q_b[3]_clock_0, , , WB2_q_b[3]_clock_enable_0);
WB2_q_b[3]_PORT_B_read_enable = VCC;
WB2_q_b[3]_PORT_B_read_enable_reg = DFFE(WB2_q_b[3]_PORT_B_read_enable, WB2_q_b[3]_clock_1, , , WB2_q_b[3]_clock_enable_1);
WB2_q_b[3]_clock_0 = L1L1;
WB2_q_b[3]_clock_1 = C1_clk_odd;
WB2_q_b[3]_clock_enable_0 = GND;
WB2_q_b[3]_clock_enable_1 = D1_ram2_ren;
WB2_q_b[3]_PORT_B_data_out = MEMORY(WB2_q_b[3]_PORT_A_data_in_reg, , WB2_q_b[3]_PORT_A_address_reg, WB2_q_b[3]_PORT_B_address_reg, WB2_q_b[3]_PORT_A_write_enable_reg, WB2_q_b[3]_PORT_B_read_enable_reg, , , WB2_q_b[3]_clock_0, WB2_q_b[3]_clock_1, WB2_q_b[3]_clock_enable_0, WB2_q_b[3]_clock_enable_1, , );
WB2_q_b[3]_PORT_B_data_out_reg = DFFE(WB2_q_b[3]_PORT_B_data_out, WB2_q_b[3]_clock_1, , , WB2_q_b[3]_clock_enable_1);
WB2_q_b[27] = WB2_q_b[3]_PORT_B_data_out_reg[6];

--WB2_q_b[31] is ram_4_32:inst24|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[31]
WB2_q_b[3]_PORT_A_data_in = sd2_dat[3];
WB2_q_b[3]_PORT_A_data_in_reg = DFFE(WB2_q_b[3]_PORT_A_data_in, WB2_q_b[3]_clock_0, , , WB2_q_b[3]_clock_enable_0);
WB2_q_b[3]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB2_q_b[3]_PORT_A_address_reg = DFFE(WB2_q_b[3]_PORT_A_address, WB2_q_b[3]_clock_0, , , WB2_q_b[3]_clock_enable_0);
WB2_q_b[3]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB2_q_b[3]_PORT_B_address_reg = DFFE(WB2_q_b[3]_PORT_B_address, WB2_q_b[3]_clock_1, , , WB2_q_b[3]_clock_enable_1);
WB2_q_b[3]_PORT_A_write_enable = VCC;
WB2_q_b[3]_PORT_A_write_enable_reg = DFFE(WB2_q_b[3]_PORT_A_write_enable, WB2_q_b[3]_clock_0, , , WB2_q_b[3]_clock_enable_0);
WB2_q_b[3]_PORT_B_read_enable = VCC;
WB2_q_b[3]_PORT_B_read_enable_reg = DFFE(WB2_q_b[3]_PORT_B_read_enable, WB2_q_b[3]_clock_1, , , WB2_q_b[3]_clock_enable_1);
WB2_q_b[3]_clock_0 = L1L1;
WB2_q_b[3]_clock_1 = C1_clk_odd;
WB2_q_b[3]_clock_enable_0 = GND;
WB2_q_b[3]_clock_enable_1 = D1_ram2_ren;
WB2_q_b[3]_PORT_B_data_out = MEMORY(WB2_q_b[3]_PORT_A_data_in_reg, , WB2_q_b[3]_PORT_A_address_reg, WB2_q_b[3]_PORT_B_address_reg, WB2_q_b[3]_PORT_A_write_enable_reg, WB2_q_b[3]_PORT_B_read_enable_reg, , , WB2_q_b[3]_clock_0, WB2_q_b[3]_clock_1, WB2_q_b[3]_clock_enable_0, WB2_q_b[3]_clock_enable_1, , );
WB2_q_b[3]_PORT_B_data_out_reg = DFFE(WB2_q_b[3]_PORT_B_data_out, WB2_q_b[3]_clock_1, , , WB2_q_b[3]_clock_enable_1);
WB2_q_b[31] = WB2_q_b[3]_PORT_B_data_out_reg[7];


--D1_ram1_ren is sd_control:inst|ram1_ren
D1_ram1_ren = DFFEAS(D1L203, !L1L1,  ,  , D1L903,  ,  ,  ,  );


--CC1L23 is mux_2bus:inst10|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|w_result385w~11
CC1L23 = D1_ram1_ren & WB1_q_b[31] # !D1_ram1_ren & (WB2_q_b[31]);


--WB1_q_b[2] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 16, Port B Width: 8
--Port A Logical Depth: 128, Port A Logical Width: 4, Port B Logical Depth: 16, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
WB1_q_b[2]_PORT_A_data_in = sd2_dat[2];
WB1_q_b[2]_PORT_A_data_in_reg = DFFE(WB1_q_b[2]_PORT_A_data_in, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[2]_PORT_A_address_reg = DFFE(WB1_q_b[2]_PORT_A_address, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[2]_PORT_B_address_reg = DFFE(WB1_q_b[2]_PORT_B_address, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_PORT_A_write_enable = VCC;
WB1_q_b[2]_PORT_A_write_enable_reg = DFFE(WB1_q_b[2]_PORT_A_write_enable, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_read_enable = VCC;
WB1_q_b[2]_PORT_B_read_enable_reg = DFFE(WB1_q_b[2]_PORT_B_read_enable, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_clock_0 = L1L1;
WB1_q_b[2]_clock_1 = C1_clk_odd;
WB1_q_b[2]_clock_enable_0 = GND;
WB1_q_b[2]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[2]_PORT_B_data_out = MEMORY(WB1_q_b[2]_PORT_A_data_in_reg, , WB1_q_b[2]_PORT_A_address_reg, WB1_q_b[2]_PORT_B_address_reg, WB1_q_b[2]_PORT_A_write_enable_reg, WB1_q_b[2]_PORT_B_read_enable_reg, , , WB1_q_b[2]_clock_0, WB1_q_b[2]_clock_1, WB1_q_b[2]_clock_enable_0, WB1_q_b[2]_clock_enable_1, , );
WB1_q_b[2]_PORT_B_data_out_reg = DFFE(WB1_q_b[2]_PORT_B_data_out, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2] = WB1_q_b[2]_PORT_B_data_out_reg[0];

--WB1_q_b[6] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[6]
WB1_q_b[2]_PORT_A_data_in = sd2_dat[2];
WB1_q_b[2]_PORT_A_data_in_reg = DFFE(WB1_q_b[2]_PORT_A_data_in, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[2]_PORT_A_address_reg = DFFE(WB1_q_b[2]_PORT_A_address, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[2]_PORT_B_address_reg = DFFE(WB1_q_b[2]_PORT_B_address, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_PORT_A_write_enable = VCC;
WB1_q_b[2]_PORT_A_write_enable_reg = DFFE(WB1_q_b[2]_PORT_A_write_enable, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_read_enable = VCC;
WB1_q_b[2]_PORT_B_read_enable_reg = DFFE(WB1_q_b[2]_PORT_B_read_enable, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_clock_0 = L1L1;
WB1_q_b[2]_clock_1 = C1_clk_odd;
WB1_q_b[2]_clock_enable_0 = GND;
WB1_q_b[2]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[2]_PORT_B_data_out = MEMORY(WB1_q_b[2]_PORT_A_data_in_reg, , WB1_q_b[2]_PORT_A_address_reg, WB1_q_b[2]_PORT_B_address_reg, WB1_q_b[2]_PORT_A_write_enable_reg, WB1_q_b[2]_PORT_B_read_enable_reg, , , WB1_q_b[2]_clock_0, WB1_q_b[2]_clock_1, WB1_q_b[2]_clock_enable_0, WB1_q_b[2]_clock_enable_1, , );
WB1_q_b[2]_PORT_B_data_out_reg = DFFE(WB1_q_b[2]_PORT_B_data_out, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[6] = WB1_q_b[2]_PORT_B_data_out_reg[1];

--WB1_q_b[10] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[10]
WB1_q_b[2]_PORT_A_data_in = sd2_dat[2];
WB1_q_b[2]_PORT_A_data_in_reg = DFFE(WB1_q_b[2]_PORT_A_data_in, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[2]_PORT_A_address_reg = DFFE(WB1_q_b[2]_PORT_A_address, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[2]_PORT_B_address_reg = DFFE(WB1_q_b[2]_PORT_B_address, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_PORT_A_write_enable = VCC;
WB1_q_b[2]_PORT_A_write_enable_reg = DFFE(WB1_q_b[2]_PORT_A_write_enable, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_read_enable = VCC;
WB1_q_b[2]_PORT_B_read_enable_reg = DFFE(WB1_q_b[2]_PORT_B_read_enable, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_clock_0 = L1L1;
WB1_q_b[2]_clock_1 = C1_clk_odd;
WB1_q_b[2]_clock_enable_0 = GND;
WB1_q_b[2]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[2]_PORT_B_data_out = MEMORY(WB1_q_b[2]_PORT_A_data_in_reg, , WB1_q_b[2]_PORT_A_address_reg, WB1_q_b[2]_PORT_B_address_reg, WB1_q_b[2]_PORT_A_write_enable_reg, WB1_q_b[2]_PORT_B_read_enable_reg, , , WB1_q_b[2]_clock_0, WB1_q_b[2]_clock_1, WB1_q_b[2]_clock_enable_0, WB1_q_b[2]_clock_enable_1, , );
WB1_q_b[2]_PORT_B_data_out_reg = DFFE(WB1_q_b[2]_PORT_B_data_out, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[10] = WB1_q_b[2]_PORT_B_data_out_reg[2];

--WB1_q_b[14] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[14]
WB1_q_b[2]_PORT_A_data_in = sd2_dat[2];
WB1_q_b[2]_PORT_A_data_in_reg = DFFE(WB1_q_b[2]_PORT_A_data_in, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[2]_PORT_A_address_reg = DFFE(WB1_q_b[2]_PORT_A_address, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[2]_PORT_B_address_reg = DFFE(WB1_q_b[2]_PORT_B_address, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_PORT_A_write_enable = VCC;
WB1_q_b[2]_PORT_A_write_enable_reg = DFFE(WB1_q_b[2]_PORT_A_write_enable, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_read_enable = VCC;
WB1_q_b[2]_PORT_B_read_enable_reg = DFFE(WB1_q_b[2]_PORT_B_read_enable, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_clock_0 = L1L1;
WB1_q_b[2]_clock_1 = C1_clk_odd;
WB1_q_b[2]_clock_enable_0 = GND;
WB1_q_b[2]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[2]_PORT_B_data_out = MEMORY(WB1_q_b[2]_PORT_A_data_in_reg, , WB1_q_b[2]_PORT_A_address_reg, WB1_q_b[2]_PORT_B_address_reg, WB1_q_b[2]_PORT_A_write_enable_reg, WB1_q_b[2]_PORT_B_read_enable_reg, , , WB1_q_b[2]_clock_0, WB1_q_b[2]_clock_1, WB1_q_b[2]_clock_enable_0, WB1_q_b[2]_clock_enable_1, , );
WB1_q_b[2]_PORT_B_data_out_reg = DFFE(WB1_q_b[2]_PORT_B_data_out, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[14] = WB1_q_b[2]_PORT_B_data_out_reg[3];

--WB1_q_b[18] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[18]
WB1_q_b[2]_PORT_A_data_in = sd2_dat[2];
WB1_q_b[2]_PORT_A_data_in_reg = DFFE(WB1_q_b[2]_PORT_A_data_in, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[2]_PORT_A_address_reg = DFFE(WB1_q_b[2]_PORT_A_address, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[2]_PORT_B_address_reg = DFFE(WB1_q_b[2]_PORT_B_address, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_PORT_A_write_enable = VCC;
WB1_q_b[2]_PORT_A_write_enable_reg = DFFE(WB1_q_b[2]_PORT_A_write_enable, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_B_read_enable = VCC;
WB1_q_b[2]_PORT_B_read_enable_reg = DFFE(WB1_q_b[2]_PORT_B_read_enable, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[2]_clock_0 = L1L1;
WB1_q_b[2]_clock_1 = C1_clk_odd;
WB1_q_b[2]_clock_enable_0 = GND;
WB1_q_b[2]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[2]_PORT_B_data_out = MEMORY(WB1_q_b[2]_PORT_A_data_in_reg, , WB1_q_b[2]_PORT_A_address_reg, WB1_q_b[2]_PORT_B_address_reg, WB1_q_b[2]_PORT_A_write_enable_reg, WB1_q_b[2]_PORT_B_read_enable_reg, , , WB1_q_b[2]_clock_0, WB1_q_b[2]_clock_1, WB1_q_b[2]_clock_enable_0, WB1_q_b[2]_clock_enable_1, , );
WB1_q_b[2]_PORT_B_data_out_reg = DFFE(WB1_q_b[2]_PORT_B_data_out, WB1_q_b[2]_clock_1, , , WB1_q_b[2]_clock_enable_1);
WB1_q_b[18] = WB1_q_b[2]_PORT_B_data_out_reg[4];

--WB1_q_b[22] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[22]
WB1_q_b[2]_PORT_A_data_in = sd2_dat[2];
WB1_q_b[2]_PORT_A_data_in_reg = DFFE(WB1_q_b[2]_PORT_A_data_in, WB1_q_b[2]_clock_0, , , WB1_q_b[2]_clock_enable_0);
WB1_q_b[2]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);