test.map.eqn

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

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--C3_clk_odd is initial_block:inst9|odd_division:clk_50m_25m|clk_odd
C3_clk_odd = DFFEAS(C3L5, sd_clk_in,  ,  , C3L3,  ,  ,  ,  );


--YB1_initial_done is initial_block:inst9|get_response:inst3|initial_done
YB1_initial_done = DFFEAS(YB1L854, C3_clk_odd,  ,  ,  ,  ,  , !vp,  );


--L1L1 is mux_2_1:inst16|out~8
L1L1 = YB1_initial_done & sd_clk_in # !YB1_initial_done & (C3_clk_odd);


--C1_clk_odd is odd_division:clk_50m_5m|clk_odd
C1_clk_odd = DFFEAS(C1L4, sd_clk_in,  ,  , C1L2,  ,  ,  ,  );


--P1_fifo_wen is fifo_control:inst26|fifo_wen
P1_fifo_wen = DFFEAS(P1_fifo_wen_temp, C1_clk_odd,  ,  ,  ,  ,  ,  ,  );


--M1_pulse is confirmpulse:inst18|pulse
M1_pulse = DFFEAS(M1L24, !L1L1,  ,  ,  ,  ,  ,  ,  );


--WB1_q_b[3] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 16, Port B Width: 8
--Port A Logical Depth: 128, Port A Logical Width: 4, Port B Logical Depth: 16, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
WB1_q_b[3]_PORT_A_data_in = sd2_dat[3];
WB1_q_b[3]_PORT_A_data_in_reg = DFFE(WB1_q_b[3]_PORT_A_data_in, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[3]_PORT_A_address_reg = DFFE(WB1_q_b[3]_PORT_A_address, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[3]_PORT_B_address_reg = DFFE(WB1_q_b[3]_PORT_B_address, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_PORT_A_write_enable = VCC;
WB1_q_b[3]_PORT_A_write_enable_reg = DFFE(WB1_q_b[3]_PORT_A_write_enable, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_read_enable = VCC;
WB1_q_b[3]_PORT_B_read_enable_reg = DFFE(WB1_q_b[3]_PORT_B_read_enable, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_clock_0 = L1L1;
WB1_q_b[3]_clock_1 = C1_clk_odd;
WB1_q_b[3]_clock_enable_0 = GND;
WB1_q_b[3]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[3]_PORT_B_data_out = MEMORY(WB1_q_b[3]_PORT_A_data_in_reg, , WB1_q_b[3]_PORT_A_address_reg, WB1_q_b[3]_PORT_B_address_reg, WB1_q_b[3]_PORT_A_write_enable_reg, WB1_q_b[3]_PORT_B_read_enable_reg, , , WB1_q_b[3]_clock_0, WB1_q_b[3]_clock_1, WB1_q_b[3]_clock_enable_0, WB1_q_b[3]_clock_enable_1, , );
WB1_q_b[3]_PORT_B_data_out_reg = DFFE(WB1_q_b[3]_PORT_B_data_out, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3] = WB1_q_b[3]_PORT_B_data_out_reg[0];

--WB1_q_b[7] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[7]
WB1_q_b[3]_PORT_A_data_in = sd2_dat[3];
WB1_q_b[3]_PORT_A_data_in_reg = DFFE(WB1_q_b[3]_PORT_A_data_in, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[3]_PORT_A_address_reg = DFFE(WB1_q_b[3]_PORT_A_address, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[3]_PORT_B_address_reg = DFFE(WB1_q_b[3]_PORT_B_address, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_PORT_A_write_enable = VCC;
WB1_q_b[3]_PORT_A_write_enable_reg = DFFE(WB1_q_b[3]_PORT_A_write_enable, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_read_enable = VCC;
WB1_q_b[3]_PORT_B_read_enable_reg = DFFE(WB1_q_b[3]_PORT_B_read_enable, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_clock_0 = L1L1;
WB1_q_b[3]_clock_1 = C1_clk_odd;
WB1_q_b[3]_clock_enable_0 = GND;
WB1_q_b[3]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[3]_PORT_B_data_out = MEMORY(WB1_q_b[3]_PORT_A_data_in_reg, , WB1_q_b[3]_PORT_A_address_reg, WB1_q_b[3]_PORT_B_address_reg, WB1_q_b[3]_PORT_A_write_enable_reg, WB1_q_b[3]_PORT_B_read_enable_reg, , , WB1_q_b[3]_clock_0, WB1_q_b[3]_clock_1, WB1_q_b[3]_clock_enable_0, WB1_q_b[3]_clock_enable_1, , );
WB1_q_b[3]_PORT_B_data_out_reg = DFFE(WB1_q_b[3]_PORT_B_data_out, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[7] = WB1_q_b[3]_PORT_B_data_out_reg[1];

--WB1_q_b[11] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[11]
WB1_q_b[3]_PORT_A_data_in = sd2_dat[3];
WB1_q_b[3]_PORT_A_data_in_reg = DFFE(WB1_q_b[3]_PORT_A_data_in, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[3]_PORT_A_address_reg = DFFE(WB1_q_b[3]_PORT_A_address, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[3]_PORT_B_address_reg = DFFE(WB1_q_b[3]_PORT_B_address, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_PORT_A_write_enable = VCC;
WB1_q_b[3]_PORT_A_write_enable_reg = DFFE(WB1_q_b[3]_PORT_A_write_enable, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_read_enable = VCC;
WB1_q_b[3]_PORT_B_read_enable_reg = DFFE(WB1_q_b[3]_PORT_B_read_enable, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_clock_0 = L1L1;
WB1_q_b[3]_clock_1 = C1_clk_odd;
WB1_q_b[3]_clock_enable_0 = GND;
WB1_q_b[3]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[3]_PORT_B_data_out = MEMORY(WB1_q_b[3]_PORT_A_data_in_reg, , WB1_q_b[3]_PORT_A_address_reg, WB1_q_b[3]_PORT_B_address_reg, WB1_q_b[3]_PORT_A_write_enable_reg, WB1_q_b[3]_PORT_B_read_enable_reg, , , WB1_q_b[3]_clock_0, WB1_q_b[3]_clock_1, WB1_q_b[3]_clock_enable_0, WB1_q_b[3]_clock_enable_1, , );
WB1_q_b[3]_PORT_B_data_out_reg = DFFE(WB1_q_b[3]_PORT_B_data_out, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[11] = WB1_q_b[3]_PORT_B_data_out_reg[2];

--WB1_q_b[15] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[15]
WB1_q_b[3]_PORT_A_data_in = sd2_dat[3];
WB1_q_b[3]_PORT_A_data_in_reg = DFFE(WB1_q_b[3]_PORT_A_data_in, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[3]_PORT_A_address_reg = DFFE(WB1_q_b[3]_PORT_A_address, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[3]_PORT_B_address_reg = DFFE(WB1_q_b[3]_PORT_B_address, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_PORT_A_write_enable = VCC;
WB1_q_b[3]_PORT_A_write_enable_reg = DFFE(WB1_q_b[3]_PORT_A_write_enable, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_read_enable = VCC;
WB1_q_b[3]_PORT_B_read_enable_reg = DFFE(WB1_q_b[3]_PORT_B_read_enable, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_clock_0 = L1L1;
WB1_q_b[3]_clock_1 = C1_clk_odd;
WB1_q_b[3]_clock_enable_0 = GND;
WB1_q_b[3]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[3]_PORT_B_data_out = MEMORY(WB1_q_b[3]_PORT_A_data_in_reg, , WB1_q_b[3]_PORT_A_address_reg, WB1_q_b[3]_PORT_B_address_reg, WB1_q_b[3]_PORT_A_write_enable_reg, WB1_q_b[3]_PORT_B_read_enable_reg, , , WB1_q_b[3]_clock_0, WB1_q_b[3]_clock_1, WB1_q_b[3]_clock_enable_0, WB1_q_b[3]_clock_enable_1, , );
WB1_q_b[3]_PORT_B_data_out_reg = DFFE(WB1_q_b[3]_PORT_B_data_out, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[15] = WB1_q_b[3]_PORT_B_data_out_reg[3];

--WB1_q_b[19] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[19]
WB1_q_b[3]_PORT_A_data_in = sd2_dat[3];
WB1_q_b[3]_PORT_A_data_in_reg = DFFE(WB1_q_b[3]_PORT_A_data_in, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[3]_PORT_A_address_reg = DFFE(WB1_q_b[3]_PORT_A_address, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[3]_PORT_B_address_reg = DFFE(WB1_q_b[3]_PORT_B_address, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_PORT_A_write_enable = VCC;
WB1_q_b[3]_PORT_A_write_enable_reg = DFFE(WB1_q_b[3]_PORT_A_write_enable, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_read_enable = VCC;
WB1_q_b[3]_PORT_B_read_enable_reg = DFFE(WB1_q_b[3]_PORT_B_read_enable, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_clock_0 = L1L1;
WB1_q_b[3]_clock_1 = C1_clk_odd;
WB1_q_b[3]_clock_enable_0 = GND;
WB1_q_b[3]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[3]_PORT_B_data_out = MEMORY(WB1_q_b[3]_PORT_A_data_in_reg, , WB1_q_b[3]_PORT_A_address_reg, WB1_q_b[3]_PORT_B_address_reg, WB1_q_b[3]_PORT_A_write_enable_reg, WB1_q_b[3]_PORT_B_read_enable_reg, , , WB1_q_b[3]_clock_0, WB1_q_b[3]_clock_1, WB1_q_b[3]_clock_enable_0, WB1_q_b[3]_clock_enable_1, , );
WB1_q_b[3]_PORT_B_data_out_reg = DFFE(WB1_q_b[3]_PORT_B_data_out, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[19] = WB1_q_b[3]_PORT_B_data_out_reg[4];

--WB1_q_b[23] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[23]
WB1_q_b[3]_PORT_A_data_in = sd2_dat[3];
WB1_q_b[3]_PORT_A_data_in_reg = DFFE(WB1_q_b[3]_PORT_A_data_in, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[3]_PORT_A_address_reg = DFFE(WB1_q_b[3]_PORT_A_address, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[3]_PORT_B_address_reg = DFFE(WB1_q_b[3]_PORT_B_address, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_PORT_A_write_enable = VCC;
WB1_q_b[3]_PORT_A_write_enable_reg = DFFE(WB1_q_b[3]_PORT_A_write_enable, WB1_q_b[3]_clock_0, , , WB1_q_b[3]_clock_enable_0);
WB1_q_b[3]_PORT_B_read_enable = VCC;
WB1_q_b[3]_PORT_B_read_enable_reg = DFFE(WB1_q_b[3]_PORT_B_read_enable, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[3]_clock_0 = L1L1;
WB1_q_b[3]_clock_1 = C1_clk_odd;
WB1_q_b[3]_clock_enable_0 = GND;
WB1_q_b[3]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[3]_PORT_B_data_out = MEMORY(WB1_q_b[3]_PORT_A_data_in_reg, , WB1_q_b[3]_PORT_A_address_reg, WB1_q_b[3]_PORT_B_address_reg, WB1_q_b[3]_PORT_A_write_enable_reg, WB1_q_b[3]_PORT_B_read_enable_reg, , , WB1_q_b[3]_clock_0, WB1_q_b[3]_clock_1, WB1_q_b[3]_clock_enable_0, WB1_q_b[3]_clock_enable_1, , );
WB1_q_b[3]_PORT_B_data_out_reg = DFFE(WB1_q_b[3]_PORT_B_data_out, WB1_q_b[3]_clock_1, , , WB1_q_b[3]_clock_enable_1);
WB1_q_b[23] = WB1_q_b[3]_PORT_B_data_out_reg[5];