tee.v

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

module tee(en,dat,out,clk);
input  [3:0]dat;
input   clk,en;
output out;
reg out,fifo_ren;
always @(posedge clk)
   begin
   if(!en)
		out<=1'b0;
	else
		begin
		if(dat==0)
			out<=1'b1;
		end
	end

endmodule