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📄 test.fit.eqn

📁 基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码
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WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[15] = WB1_q_b[0]_PORT_B_data_out_reg[15];

--WB1_q_b[14] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[14] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[14] = WB1_q_b[0]_PORT_B_data_out_reg[14];

--WB1_q_b[13] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[13] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[13] = WB1_q_b[0]_PORT_B_data_out_reg[13];

--WB1_q_b[11] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[11] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[11] = WB1_q_b[0]_PORT_B_data_out_reg[11];

--WB1_q_b[10] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[10] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[10] = WB1_q_b[0]_PORT_B_data_out_reg[10];

--WB1_q_b[9] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[9] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[9] = WB1_q_b[0]_PORT_B_data_out_reg[9];

--WB1_q_b[7] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[7] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[7] = WB1_q_b[0]_PORT_B_data_out_reg[7];

--WB1_q_b[6] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[6] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[6] = WB1_q_b[0]_PORT_B_data_out_reg[6];
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