test.fit.eqn

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C3_clk_odd is initial_block:inst9|odd_division:clk_50m_25m|clk_odd at LCFF_X50_Y33_N31
C3_clk_odd = DFFEAS(C3L5, GLOBAL(A1L402),  ,  , C3L3,  ,  ,  ,  );


--YB1_initial_done is initial_block:inst9|get_response:inst3|initial_done at LCFF_X47_Y29_N13
YB1_initial_done = DFFEAS(YB1L854, GLOBAL(C3L6),  ,  ,  ,  ,  , !vp,  );


--L1L1 is mux_2_1:inst16|out~8 at LCCOMB_X50_Y33_N0
L1L1 = YB1_initial_done & sd_clk_in # !YB1_initial_done & (C3_clk_odd);


--C1_clk_odd is odd_division:clk_50m_5m|clk_odd at LCFF_X64_Y21_N29
C1_clk_odd = DFFEAS(C1L4, GLOBAL(A1L402),  ,  , C1L2,  ,  ,  ,  );


--P1_fifo_wen is fifo_control:inst26|fifo_wen at LCFF_X48_Y30_N9
P1_fifo_wen = DFFEAS(P1L42, GLOBAL(C1L5),  ,  ,  ,  ,  ,  ,  );


--M1_pulse is confirmpulse:inst18|pulse at LCFF_X49_Y33_N19
M1_pulse = DFFEAS(M1L24, !GLOBAL(L1L2),  ,  ,  ,  ,  ,  ,  );


--D1_ram1_ren is sd_control:inst|ram1_ren at LCFF_X51_Y28_N31
D1_ram1_ren = DFFEAS(D1L203, !GLOBAL(L1L2),  ,  , D1L903,  ,  ,  ,  );


--CC1L23 is mux_2bus:inst10|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|w_result385w~11 at LCCOMB_X51_Y28_N20
CC1L23 = D1_ram1_ren & WB1_q_b[31] # !D1_ram1_ren & (WB2_q_b[31]);


--CC1L13 is mux_2bus:inst10|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|w_result373w~11 at LCCOMB_X51_Y28_N24
CC1L13 = D1_ram1_ren & WB1_q_b[30] # !D1_ram1_ren & (WB2_q_b[30]);


--CC1L03 is mux_2bus:inst10|lpm_mux:lpm_mux_component|mux_9oc:auto_generated|w_result361w~11 at LCCOMB_X51_Y28_N4
CC1L03 = D1_ram1_ren & WB1_q_b[29] # !D1_ram1_ren & (WB2_q_b[29]);


--WB1_q_b[0] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[0] at M4K_X52_Y29
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 4, Port B Depth: 16, Port B Width: 32
--Port A Logical Depth: 128, Port A Logical Width: 4, Port B Logical Depth: 16, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0] = WB1_q_b[0]_PORT_B_data_out_reg[0];

--WB1_q_b[4] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[4] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[4] = WB1_q_b[0]_PORT_B_data_out_reg[4];

--WB1_q_b[8] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[8] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[8] = WB1_q_b[0]_PORT_B_data_out_reg[8];

--WB1_q_b[12] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[12] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;
WB1_q_b[0]_clock_enable_1 = D1_ram1_ren;
WB1_q_b[0]_PORT_B_data_out = MEMORY(WB1_q_b[0]_PORT_A_data_in_reg, , WB1_q_b[0]_PORT_A_address_reg, WB1_q_b[0]_PORT_B_address_reg, WB1_q_b[0]_PORT_A_write_enable_reg, WB1_q_b[0]_PORT_B_read_enable_reg, , , WB1_q_b[0]_clock_0, WB1_q_b[0]_clock_1, WB1_q_b[0]_clock_enable_0, WB1_q_b[0]_clock_enable_1, , );
WB1_q_b[0]_PORT_B_data_out_reg = DFFE(WB1_q_b[0]_PORT_B_data_out, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[12] = WB1_q_b[0]_PORT_B_data_out_reg[12];

--WB1_q_b[16] is ram_4_32:inst1|altsyncram:altsyncram_component|altsyncram_c9h1:auto_generated|q_b[16] at M4K_X52_Y29
WB1_q_b[0]_PORT_A_data_in = BUS(sd2_dat[0], sd2_dat[1], sd2_dat[2], sd2_dat[3]);
WB1_q_b[0]_PORT_A_data_in_reg = DFFE(WB1_q_b[0]_PORT_A_data_in, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_A_address = BUS(D1_ram_address[0], D1_ram_address[1], D1_ram_address[2], D1_ram_address[3], D1_ram_address[4], D1_ram_address[5], D1_ram_address[6]);
WB1_q_b[0]_PORT_A_address_reg = DFFE(WB1_q_b[0]_PORT_A_address, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_address = BUS(P1_address[0], P1_address[1], P1_address[2], P1_address[3]);
WB1_q_b[0]_PORT_B_address_reg = DFFE(WB1_q_b[0]_PORT_B_address, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_PORT_A_write_enable = VCC;
WB1_q_b[0]_PORT_A_write_enable_reg = DFFE(WB1_q_b[0]_PORT_A_write_enable, WB1_q_b[0]_clock_0, , , WB1_q_b[0]_clock_enable_0);
WB1_q_b[0]_PORT_B_read_enable = VCC;
WB1_q_b[0]_PORT_B_read_enable_reg = DFFE(WB1_q_b[0]_PORT_B_read_enable, WB1_q_b[0]_clock_1, , , WB1_q_b[0]_clock_enable_1);
WB1_q_b[0]_clock_0 = GLOBAL(L1L2);
WB1_q_b[0]_clock_1 = GLOBAL(C1L5);
WB1_q_b[0]_clock_enable_0 = GND;