test.qsf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		test_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:18:46  SEPTEMBER 26, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_parameter -name CYCLONEII_SAFE_WRITE RESTRUCTURE
set_global_assignment -name SIGNALTAP_FILE test.stp
set_global_assignment -name BDF_FILE test.bdf
set_global_assignment -name VERILOG_FILE confirmpulse.v
set_global_assignment -name VERILOG_FILE get_response.v
set_global_assignment -name VERILOG_FILE odd_division.v
set_global_assignment -name VERILOG_FILE sd_initial.v
set_global_assignment -name VERILOG_FILE send_cmd.v
set_global_assignment -name VERILOG_FILE shift_r1.v
set_global_assignment -name VERILOG_FILE shift_reg.v
set_global_assignment -name VERILOG_FILE timer.v
set_global_assignment -name VERILOG_FILE bidirec.v
set_global_assignment -name VERILOG_FILE wipe_off_burr.v
set_global_assignment -name BDF_FILE initial_block.bdf
set_global_assignment -name VERILOG_FILE mux_2_1.v
set_global_assignment -name VERILOG_FILE sd_control.v
set_global_assignment -name VERILOG_FILE te.v
set_global_assignment -name MIF_FILE test.mif
set_global_assignment -name VERILOG_FILE tee.v

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_A12 -to sd_clk_in
set_location_assignment PIN_E14 -to al_da_ram
set_location_assignment PIN_L22 -to clk75m
set_location_assignment PIN_A4 -to fifo1_d[0]
set_location_assignment PIN_B4 -to fifo1_d[1]
set_location_assignment PIN_A5 -to fifo1_d[2]
set_location_assignment PIN_B5 -to fifo1_d[3]
set_location_assignment PIN_A6 -to fifo1_d[4]
set_location_assignment PIN_B6 -to fifo1_d[5]
set_location_assignment PIN_A7 -to fifo1_d[6]
set_location_assignment PIN_B7 -to fifo1_d[7]
set_location_assignment PIN_C7 -to fifo1_d[8]
set_location_assignment PIN_A8 -to fifo1_d[9]
set_location_assignment PIN_B8 -to fifo1_d[10]
set_location_assignment PIN_D8 -to fifo1_d[11]
set_location_assignment PIN_A9 -to fifo1_d[12]
set_location_assignment PIN_B9 -to fifo1_d[13]
set_location_assignment PIN_C9 -to fifo1_d[14]
set_location_assignment PIN_D9 -to fifo1_d[15]
set_location_assignment PIN_A10 -to fifo1_d[16]
set_location_assignment PIN_B10 -to fifo1_d[17]
set_location_assignment PIN_C10 -to fifo1_d[18]
set_location_assignment PIN_A11 -to fifo1_d[19]
set_location_assignment PIN_B11 -to fifo1_d[20]
set_location_assignment PIN_D11 -to fifo1_d[21]
set_location_assignment PIN_A13 -to fifo1_d[22]
set_location_assignment PIN_B13 -to fifo1_d[23]
set_location_assignment PIN_C13 -to fifo1_d[24]
set_location_assignment PIN_A14 -to fifo1_d[25]
set_location_assignment PIN_B14 -to fifo1_d[26]
set_location_assignment PIN_C14 -to fifo1_d[27]
set_location_assignment PIN_D14 -to fifo1_d[28]
set_location_assignment PIN_A15 -to fifo1_d[29]
set_location_assignment PIN_B15 -to fifo1_d[30]
set_location_assignment PIN_D15 -to fifo1_d[31]
set_location_assignment PIN_D3 -to fifo1_ef
set_location_assignment PIN_C16 -to fifo1_rclk
set_location_assignment PIN_A18 -to fifo1_wclk
set_location_assignment PIN_A19 -to fifo2_d[0]
set_location_assignment PIN_B19 -to fifo2_d[1]
set_location_assignment PIN_C19 -to fifo2_d[2]
set_location_assignment PIN_C20 -to fifo2_d[3]
set_location_assignment PIN_A20 -to fifo2_d[4]
set_location_assignment PIN_B20 -to fifo2_d[5]
set_location_assignment PIN_D19 -to fifo2_d[6]
set_location_assignment PIN_D20 -to fifo2_d[7]
set_location_assignment PIN_C21 -to fifo2_d[8]
set_location_assignment PIN_C22 -to fifo2_d[9]
set_location_assignment PIN_D21 -to fifo2_d[10]
set_location_assignment PIN_D22 -to fifo2_d[11]
set_location_assignment PIN_E19 -to fifo2_d[12]
set_location_assignment PIN_E20 -to fifo2_d[13]
set_location_assignment PIN_E21 -to fifo2_d[14]
set_location_assignment PIN_E22 -to fifo2_d[15]
set_location_assignment PIN_F20 -to fifo2_d[16]
set_location_assignment PIN_F21 -to fifo2_d[17]
set_location_assignment PIN_F22 -to fifo2_d[18]
set_location_assignment PIN_G20 -to fifo2_d[19]
set_location_assignment PIN_G21 -to fifo2_d[20]
set_location_assignment PIN_G22 -to fifo2_d[21]
set_location_assignment PIN_H19 -to fifo2_d[22]
set_location_assignment PIN_H21 -to fifo2_d[23]
set_location_assignment PIN_H22 -to fifo2_d[24]
set_location_assignment PIN_J19 -to fifo2_d[25]
set_location_assignment PIN_J20 -to fifo2_d[26]
set_location_assignment PIN_J21 -to fifo2_d[27]
set_location_assignment PIN_J22 -to fifo2_d[28]
set_location_assignment PIN_K20 -to fifo2_d[29]
set_location_assignment PIN_K21 -to fifo2_d[30]
set_location_assignment PIN_K22 -to fifo2_d[31]
set_location_assignment PIN_G18 -to fifo2_ef
set_location_assignment PIN_D16 -to fifo2_rclk
set_location_assignment PIN_B18 -to fifo2_wclk
set_location_assignment PIN_N21 -to fifo3_d[0]
set_location_assignment PIN_N22 -to fifo3_d[1]
set_location_assignment PIN_P19 -to fifo3_d[2]
set_location_assignment PIN_P20 -to fifo3_d[3]
set_location_assignment PIN_P21 -to fifo3_d[4]
set_location_assignment PIN_P22 -to fifo3_d[5]
set_location_assignment PIN_R19 -to fifo3_d[6]
set_location_assignment PIN_R20 -to fifo3_d[7]
set_location_assignment PIN_R21 -to fifo3_d[8]
set_location_assignment PIN_R22 -to fifo3_d[9]
set_location_assignment PIN_T18 -to fifo3_d[10]
set_location_assignment PIN_T21 -to fifo3_d[11]
set_location_assignment PIN_T22 -to fifo3_d[12]
set_location_assignment PIN_U20 -to fifo3_d[13]
set_location_assignment PIN_U19 -to fifo3_d[14]
set_location_assignment PIN_V20 -to fifo3_d[15]
set_location_assignment PIN_U21 -to fifo3_d[16]
set_location_assignment PIN_U22 -to fifo3_d[17]
set_location_assignment PIN_W20 -to fifo3_d[18]
set_location_assignment PIN_V21 -to fifo3_d[19]
set_location_assignment PIN_V22 -to fifo3_d[20]
set_location_assignment PIN_Y20 -to fifo3_d[21]
set_location_assignment PIN_W21 -to fifo3_d[22]
set_location_assignment PIN_W22 -to fifo3_d[23]
set_location_assignment PIN_Y19 -to fifo3_d[24]
set_location_assignment PIN_Y18 -to fifo3_d[25]
set_location_assignment PIN_Y21 -to fifo3_d[26]