test.stp

来自「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）」· STP 代码 · 共 85 行 · 第 1/5 页

            <net is_signal_inverted="no" name="sd2_dat[1]"/>
            <net is_signal_inverted="no" name="sd2_dat[0]"/>
          </bus>
          <net is_signal_inverted="no" name="sd2_cmd"/>
          <bus is_signal_inverted="no" link="all" name="initial_block:inst9|send_cmd:inst4|cmd_num" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="initial_block:inst9|send_cmd:inst4|cmd_num[3]"/>
            <net is_signal_inverted="no" name="initial_block:inst9|send_cmd:inst4|cmd_num[2]"/>
            <net is_signal_inverted="no" name="initial_block:inst9|send_cmd:inst4|cmd_num[1]"/>
            <net is_signal_inverted="no" name="initial_block:inst9|send_cmd:inst4|cmd_num[0]"/>
          </bus>
        </data_view>
        <setup_view>
          <bus is_signal_inverted="no" link="all" name="sd2_dat" order="msb_to_lsb" radix="hex" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="sd2_dat[3]"/>
            <net is_signal_inverted="no" name="sd2_dat[2]"/>
            <net is_signal_inverted="no" name="sd2_dat[1]"/>
            <net is_signal_inverted="no" name="sd2_dat[0]"/>