test.stp

来自「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）」· STP 代码 · 共 85 行 · 第 1/5 页

        <data_input_vec>
          <wire connection_status="true" name="initial_block:inst9|send_cmd:inst4|cmd_num[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="initial_block:inst9|send_cmd:inst4|cmd_num[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="initial_block:inst9|send_cmd:inst4|cmd_num[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="initial_block:inst9|send_cmd:inst4|cmd_num[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sd2_cmd" tap_mode="classic" type="bidir pin"/>
          <wire connection_status="true" name="sd2_dat[0]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="sd2_dat[1]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="sd2_dat[2]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="sd2_dat[3]" tap_mode="classic" type="input pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="sd2_dat" order="msb_to_lsb" radix="hex" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="sd2_dat[3]"/>
            <net is_signal_inverted="no" name="sd2_dat[2]"/>