altsyncram_9n92.tdf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a48 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 48,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 48,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a49 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 49,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 49,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a50 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 50,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 50,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a51 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 51,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 51,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a52 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 52,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 52,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a53 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 53,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 53,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a54 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 54,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 54,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a55 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 55,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 55,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a56 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 56,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 57,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 56,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 57,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[6..0]	: WIRE;
	address_b_wire[6..0]	: WIRE;

BEGIN 
	ram_block1a[56..0].clk0 = clock0;
	ram_block1a[56..0].clk1 = clock1;
	ram_block1a[56..0].ena0 = wren_a;
	ram_block1a[56..0].ena1 = clocken1;
	ram_block1a[0].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[1].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[2].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[3].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[4].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[5].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[6].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[7].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[8].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[9].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[10].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[11].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[12].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[13].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[14].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[15].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[16].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[17].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[18].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[19].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[20].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[21].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[22].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[23].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[24].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[25].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[26].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[27].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[28].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[29].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[30].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[31].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[32].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[33].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[34].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[35].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[36].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[37].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[38].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[39].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[40].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[41].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[42].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[43].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[44].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[45].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[46].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[47].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[48].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[49].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[50].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[51].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[52].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[53].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[54].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[55].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[56].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[8..8]);
	ram_block1a[9].portadatain[] = ( data_a[9..9]);
	ram_block1a[10].portadatain[] = ( data_a[10..10]);
	ram_block1a[11].portadatain[] = ( data_a[11..11]);
	ram_block1a[12].portadatain[] = ( data_a[12..12]);
	ram_block1a[13].portadatain[] = ( data_a[13..13]);
	ram_block1a[14].portadatain[] = ( data_a[14..14]);
	ram_block1a[15].portadatain[] = ( data_a[15..15]);
	ram_block1a[16].portadatain[] = ( data_a[16..16]);
	ram_block1a[17].portadatain[] = ( data_a[17..17]);
	ram_block1a[18].portadatain[] = ( data_a[18..18]);
	ram_block1a[19].portadatain[] = ( data_a[19..19]);
	ram_block1a[20].portadatain[] = ( data_a[20..20]);
	ram_block1a[21].portadatain[] = ( data_a[21..21]);
	ram_block1a[22].portadatain[] = ( data_a[22..22]);
	ram_block1a[23].portadatain[] = ( data_a[23..23]);
	ram_block1a[24].portadatain[] = ( data_a[24..24]);
	ram_block1a[25].portadatain[] = ( data_a[25..25]);
	ram_block1a[26].portadatain[] = ( data_