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📄 mux_fib.tdf

📁 基于QUARTUSII软件 实现FPGA(ATERA CYCLONE II系列)与SD卡SD模式通信源码
💻 TDF
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=6 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 6 
SUBDESIGN mux_fib
( 
	data[11..0]	:	input;
	result[5..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[5..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data113w[1..0]	: WIRE;
	w_data127w[1..0]	: WIRE;
	w_data139w[1..0]	: WIRE;
	w_data151w[1..0]	: WIRE;
	w_data163w[1..0]	: WIRE;
	w_data175w[1..0]	: WIRE;
	w_result114w	: WIRE;
	w_result120w	: WIRE;
	w_result128w	: WIRE;
	w_result134w	: WIRE;
	w_result140w	: WIRE;
	w_result146w	: WIRE;
	w_result152w	: WIRE;
	w_result158w	: WIRE;
	w_result164w	: WIRE;
	w_result170w	: WIRE;
	w_result176w	: WIRE;
	w_result182w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result176w, w_result164w, w_result152w, w_result140w, w_result128w, w_result114w);
	sel_node[] = ( sel[0..0]);
	w_data113w[] = ( data[6..6], data[0..0]);
	w_data127w[] = ( data[7..7], data[1..1]);
	w_data139w[] = ( data[8..8], data[2..2]);
	w_data151w[] = ( data[9..9], data[3..3]);
	w_data163w[] = ( data[10..10], data[4..4]);
	w_data175w[] = ( data[11..11], data[5..5]);
	w_result114w = w_result120w;
	w_result120w = ((sel_node[] & w_data113w[1..1]) # ((! sel_node[]) & w_data113w[0..0]));
	w_result128w = w_result134w;
	w_result134w = ((sel_node[] & w_data127w[1..1]) # ((! sel_node[]) & w_data127w[0..0]));
	w_result140w = w_result146w;
	w_result146w = ((sel_node[] & w_data139w[1..1]) # ((! sel_node[]) & w_data139w[0..0]));
	w_result152w = w_result158w;
	w_result158w = ((sel_node[] & w_data151w[1..1]) # ((! sel_node[]) & w_data151w[0..0]));
	w_result164w = w_result170w;
	w_result170w = ((sel_node[] & w_data163w[1..1]) # ((! sel_node[]) & w_data163w[0..0]));
	w_result176w = w_result182w;
	w_result182w = ((sel_node[] & w_data175w[1..1]) # ((! sel_node[]) & w_data175w[0..0]));
END;
--VALID FILE

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