📄 altsyncram_pm92.tdf

📁 基于QUARTUSII软件实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码
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			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 6,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 6,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a19 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 6,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 6,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a20 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 6,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 6,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a21 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 6,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 6,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a22 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 6,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 6,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a23 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 6,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 6,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[13..0]	: WIRE;
	address_b_wire[13..0]	: WIRE;

BEGIN 
	address_reg_b[].CLK = clock1;
	address_reg_b[].D = address_b[13..12];
	address_reg_b[].ENA = clocken1;
	decode2.data[1..0] = address_a_wire[13..12];
	decode2.enable = wren_a;
	mux3.data[] = ( ram_block1a[23..0].portbdataout[0..0]);
	mux3.sel[] = address_reg_b[].Q;
	ram_block1a[23..0].clk0 = clock0;
	ram_block1a[23..0].clk1 = clock1;
	ram_block1a[0].ena0 = decode2.eq[0..0];
	ram_block1a[1].ena0 = decode2.eq[0..0];
	ram_block1a[2].ena0 = decode2.eq[0..0];
	ram_block1a[3].ena0 = decode2.eq[0..0];
	ram_block1a[4].ena0 = decode2.eq[0..0];
	ram_block1a[5].ena0 = decode2.eq[0..0];
	ram_block1a[6].ena0 = decode2.eq[1..1];
	ram_block1a[7].ena0 = decode2.eq[1..1];
	ram_block1a[8].ena0 = decode2.eq[1..1];
	ram_block1a[9].ena0 = decode2.eq[1..1];
	ram_block1a[10].ena0 = decode2.eq[1..1];
	ram_block1a[11].ena0 = decode2.eq[1..1];
	ram_block1a[12].ena0 = decode2.eq[2..2];
	ram_block1a[13].ena0 = decode2.eq[2..2];
	ram_block1a[14].ena0 = decode2.eq[2..2];
	ram_block1a[15].ena0 = decode2.eq[2..2];
	ram_block1a[16].ena0 = decode2.eq[2..2];
	ram_block1a[17].ena0 = decode2.eq[2..2];
	ram_block1a[18].ena0 = decode2.eq[3..3];
	ram_block1a[19].ena0 = decode2.eq[3..3];
	ram_block1a[20].ena0 = decode2.eq[3..3];
	ram_block1a[21].ena0 = decode2.eq[3..3];
	ram_block1a[22].ena0 = decode2.eq[3..3];
	ram_block1a[23].ena0 = decode2.eq[3..3];
	ram_block1a[23..0].ena1 = clocken1;
	ram_block1a[0].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[1].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[2].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[3].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[4].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[5].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[6].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[7].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[8].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[9].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[10].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[11].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[12].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[13].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[14].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[15].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[16].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[17].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[18].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[19].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[20].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[21].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[22].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[23].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[0..0]);
	ram_block1a[7].portadatain[] = ( data_a[1..1]);
	ram_block1a[8].portadatain[] = ( data_a[2..2]);
	ram_block1a[9].portadatain[] = ( data_a[3..3]);
	ram_block1a[10].portadatain[] = ( data_a[4..4]);
	ram_block1a[11].portadatain[] = ( data_a[5..5]);
	ram_block1a[12].portadatain[] = ( data_a[0..0]);
	ram_block1a[13].portadatain[] = ( data_a[1..1]);
	ram_block1a[14].portadatain[] = ( data_a[2..2]);
	ram_block1a[15].portadatain[] = ( data_a[3..3]);
	ram_block1a[16].portadatain[] = ( data_a[4..4]);
	ram_block1a[17].portadatain[] = ( data_a[5..5]);
	ram_block1a[18].portadatain[] = ( data_a[0..0]);
	ram_block1a[19].portadatain[] = ( data_a[1..1]);
	ram_block1a[20].portadatain[] = ( data_a[2..2]);
	ram_block1a[21].portadatain[] = ( data_a[3..3]);
	ram_block1a[22].portadatain[] = ( data_a[4..4]);
	ram_block1a[23].portadatain[] = ( data_a[5..5]);
	ram_block1a[23..0].portawe = B"111111111111111111111111";
	ram_block1a[0].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[1].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[2].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[3].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[4].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[5].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[6].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[7].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[8].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[9].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[10].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[11].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[12].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[13].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[14].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[15].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[16].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[17].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[18].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[19].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[20].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[21].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[22].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[23].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[23..0].portbrewe = B"111111111111111111111111";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = mux3.result[];
END;
--VALID FILE
上一页 1 23
💿 文件大小 4946 K
👤 上传用户 wujiahui1pm
📂 所属分类教程资料
🏷️ 相关标签

#QUARTUSII #CYCLONE #ATERA #FPGA
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