altsyncram_pq92.tdf

来自「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）」· TDF 代码 · 共 1,835 行 · 第 1/5 页

TDF
1,835 行
字号
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			PORT_B_FIRST_BIT_NUMBER = 23,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a24 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 24,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a25 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 25,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a26 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 26,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a27 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 27,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a28 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 28,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a29 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 29,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a30 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 30,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a31 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 31,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a32 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 32,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 32,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a33 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 33,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 33,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a34 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 34,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 34,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a35 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 35,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 189,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 35,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 189,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a36 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 36,
			PORT_A_LAST_ADDRESS = 511,
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altsyncram_pq92.tdf - 源码说明

本页面展示了「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码」中的 altsyncram_pq92.tdf 源码文件，采用 TDF 编程语言编写，共 1,835 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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