test.map.qmsg

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_2_1 mux_2_1:inst16 " "Info: Elaborating entity \"mux_2_1\" for hierarchy \"mux_2_1:inst16\"" {  } { { "test.bdf" "inst16" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 152 1728 1824 248 "inst16" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "initial_block initial_block:inst9 " "Info: Elaborating entity \"initial_block\" for hierarchy \"initial_block:inst9\"" {  } { { "test.bdf" "inst9" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 120 1024 1232 280 "inst9" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "get_response initial_block:inst9\|get_response:inst3 " "Info: Elaborating entity \"get_response\" for hierarchy \"initial_block:inst9\|get_response:inst3\"" {  } { { "initial_block.bdf" "inst3" { Schematic "C:/altera/quartus50/workone/initial_block.bdf" { { 656 920 1128 848 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "confirmpulse initial_block:inst9\|get_response:inst3\|confirmpulse:pulse_gen " "Info: Elaborating entity \"confirmpulse\" for hierarchy \"initial_block:inst9\|get_response:inst3\|confirmpulse:pulse_gen\"" {  } { { "get_response.v" "pulse_gen" { Text "C:/altera/quartus50/workone/get_response.v" 176 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "send_cmd initial_block:inst9\|send_cmd:inst4 " "Info: Elaborating entity \"send_cmd\" for hierarchy \"initial_block:inst9\|send_cmd:inst4\"" {  } { { "initial_block.bdf" "inst4" { Schematic "C:/altera/quartus50/workone/initial_block.bdf" { { 440 904 1128 600 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "odd_division initial_block:inst9\|odd_division:clk_50m_25m " "Info: Elaborating entity \"odd_division\" for hierarchy \"initial_block:inst9\|odd_division:clk_50m_25m\"" {  } { { "initial_block.bdf" "clk_50m_25m" { Schematic "C:/altera/quartus50/workone/initial_block.bdf" { { 120 560 696 216 "clk_50m_25m" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer initial_block:inst9\|timer:inst " "Info: Elaborating entity \"timer\" for hierarchy \"initial_block:inst9\|timer:inst\"" {  } { { "initial_block.bdf" "inst" { Schematic "C:/altera/quartus50/workone/initial_block.bdf" { { 128 936 1048 224 "inst" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "crc8.vhd 2 1 " "Info: Using design file crc8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 crc8-Beh " "Info: Found design unit 1: crc8-Beh" {  } { { "crc8.vhd" "" { Text "C:/altera/quartus50/workone/crc8.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 crc8 " "Info: Found entity 1: crc8" {  } { { "crc8.vhd" "" { Text "C:/altera/quartus50/workone/crc8.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "crc8 initial_block:inst9\|crc8:inst10 " "Info: Elaborating entity \"crc8\" for hierarchy \"initial_block:inst9\|crc8:inst10\"" {  } { { "initial_block.bdf" "inst10" { Schematic "C:/altera/quartus50/workone/initial_block.bdf" { { 288 928 1096 384 "inst10" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_r1 initial_block:inst9\|shift_r1:inst5 " "Info: Elaborating entity \"shift_r1\" for hierarchy \"initial_block:inst9\|shift_r1:inst5\"" {  } { { "initial_block.bdf" "inst5" { Schematic "C:/altera/quartus50/workone/initial_block.bdf" { { 680 504 744 808 "inst5" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "n shift_r1.v(23) " "Info: (10035) Verilog HDL or VHDL information at shift_r1.v(23): object \"n\" declared but not used" {  } { { "shift_r1.v" "" { Text "C:/altera/quartus50/workone/shift_r1.v" 23 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_reg initial_block:inst9\|shift_reg:inst7 " "Info: Elaborating entity \"shift_reg\" for hierarchy \"initial_block:inst9\|shift_reg:inst7\"" {  } { { "initial_block.bdf" "inst7" { Schematic "C:/altera/quartus50/workone/initial_block.bdf" { { 376 1272 1448 504 "inst7" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bidirec bidirec:inst13 " "Info: Elaborating entity \"bidirec\" for hierarchy \"bidirec:inst13\"" {  } { { "test.bdf" "inst13" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 216 1488 1584 312 "inst13" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_control sd_control:inst " "Info: Elaborating entity \"sd_control\" for hierarchy \"sd_control:inst\"" {  } { { "test.bdf" "inst" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 400 1072 1384 624 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_reg sd_control:inst\|shift_reg:cmd18 " "Info: Elaborating entity \"shift_reg\" for hierarchy \"sd_control:inst\|shift_reg:cmd18\"" {  } { { "sd_control.v" "cmd18" { Text "C:/altera/quartus50/workone/sd_control.v" 241 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "fifo_control.v 1 1 " "Info: Using design file fifo_control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_control " "Info: Found entity 1: fifo_control" {  } { { "fifo_control.v" "" { Text "C:/altera/quartus50/workone/fifo_control.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_control fifo_control:inst26 " "Info: Elaborating entity \"fifo_control\" for hierarchy \"fifo_control:inst26\"" {  } { { "test.bdf" "inst26" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 784 1144 1360 912 "inst26" "" } } } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "fifo_control.v(47) " "Info: Verilog HDL Case Statement information at fifo_control.v(47): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "fifo_control.v" "" { Text "C:/altera/quartus50/workone/fifo_control.v" 47 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "mux_2bus.v 1 1 " "Info: Using design file mux_2bus.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mux_2bus " "Info: Found entity 1: mux_2bus" {  } { { "mux_2bus.v" "" { Text "C:/altera/quartus50/workone/mux_2bus.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_2bus mux_2bus:inst10 " "Info: Elaborating entity \"mux_2bus\" for hierarchy \"mux_2bus:inst10\"" {  } { { "test.bdf" "inst10" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 664 1928 2080 744 "inst10" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux mux_2bus:inst10\|lpm_mux:lpm_mux_component " "Info: Elaborating entity \"lpm_mux\" for hierarchy \"mux_2bus:inst10\|lpm_mux:lpm_mux_component\"" {  } { { "mux_2bus.v" "lpm_mux_component" { Text "C:/altera/quartus50/workone/mux_2bus.v" 65 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_9oc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_9oc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_9oc " "Info: Found entity 1: mux_9oc" {  } { { "db/mux_9oc.tdf" "" { Text "C:/altera/quartus50/workone/db/mux_9oc.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_9oc mux_2bus:inst10\|lpm_mux:lpm_mux_component\|mux_9oc:auto_generated " "Info: Elaborating entity \"mux_9oc\" for hierarchy \"mux_2bus:inst10\|lpm_mux:lpm_mux_component\|mux_9oc:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf" 84 3 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ram_4_32.v 1 1 " "Info: Using design file ram_4_32.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ram_4_32 " "Info: Found entity 1: ram_4_32" {  } { { "ram_4_32.v" "" { Text "C:/altera/quartus50/workone/ram_4_32.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram_4_32 ram_4_32:inst24 " "Info: Elaborating entity \"ram_4_32\" for hierarchy \"ram_4_32:inst24\"" {  } { { "test.bdf" "inst24" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 728 1632 1888 904 "inst24" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram_4_32:inst24\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ram_4_32:inst24\|altsyncram:altsyncram_component\"" {  } { { "ram_4_32.v" "altsyncram_component" { Text "C:/altera/quartus50/workone/ram_4_32.v" 81 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_c9h1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_c9h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_c9h1 " "Info: Found entity 1: altsyncram_c9h1" {  } { { "db/altsyncram_c9h1.tdf" "" { Text "C:/altera/quartus50/workone/db/altsyncram_c9h1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_c9h1 ram_4_32:inst24\|altsyncram:altsyncram_component\|altsyncram_c9h1:auto_generated " "Info: Elaborating entity \"altsyncram_c9h1\" for hierarchy \"ram_4_32:inst24\|altsyncram:altsyncram_component\|altsyncram_c9h1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "te te:inst23 " "Info: Elaborating entity \"te\" for hierarchy \"te:inst23\"" {  } { { "test.bdf" "inst23" { Schematic "C:/altera/quartus50/workone/test.bdf" { { -80 1712 1832 16 "inst23" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tee tee:inst7 " "Info: Elaborating entity \"tee\" for hierarchy \"tee:inst7\"" {  } { { "test.bdf" "inst7" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 24 1720 1832 120 "inst7" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "fifo_ren tee.v(5) " "Info: (10035) Verilog HDL or VHDL information at tee.v(5): object \"fifo_ren\" declared but not used" {  } { { "tee.v" "" { Text "C:/altera/quartus50/workone/tee.v" 5 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/sld_signaltap.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file ../libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 170 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0}  } {  } 0}