test.hif

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
OFF
PARAMETER_UNKNOWN
USR
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_h7a
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
cout
q0
q10
q11
q12
q13
q14
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|lpm_decode.inc
1107574570
..|libraries|megafunctions|dffeea.inc
1107574164
..|libraries|megafunctions|lpm_constant.inc
1107574524
..|libraries|megafunctions|lpm_add_sub.inc
1107574408
..|libraries|megafunctions|cmpconst.inc
1107573980
..|libraries|megafunctions|lpm_compare.inc
1107574500
..|libraries|megafunctions|lpm_counter.inc
1107574548
..|libraries|megafunctions|alt_synch_counter.inc
1107572664
..|libraries|megafunctions|alt_synch_counter_f.inc
1107572680
..|libraries|megafunctions|alt_counter_f10ke.inc
1107572320
..|libraries|megafunctions|alt_counter_stratix.inc
1107572334
}
# end
# entity
cntr_h7a
# case_insensitive
# source_file
db|cntr_h7a.tdf
1194058559
6
# storage
db|test.(53).cnf
db|test.(53).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
q13
q14
cout
}
# end
# entity
lpm_ff
# case_insensitive
# source_file
..|libraries|megafunctions|lpm_ff.tdf
1114012452
6
# storage
db|test.(54).cnf
db|test.(54).cnf
# user_parameter {
LPM_WIDTH
15
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FFTYPE
DFF
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data1
data2
data3
data4
data5
data6
data7
data8
data9
enable
q0
q10
q11
q12
q13
q14
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|test.(55).cnf
db|test.(55).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
5
PARAMETER_DEC
USR
WIDTHAD_A
15
PARAMETER_DEC
USR
NUMWORDS_A
1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
5
PARAMETER_DEC
USR
WIDTHAD_B
15
PARAMETER_DEC
USR
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_qm92
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a11
address_a12
address_a13
address_a14
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b10
address_b11
address_b12
address_b13
address_b14
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
clock1
clocken1
data_a0
data_a1
data_a2
data_a3
data_a4
q_b0
q_b1
q_b2
q_b3
q_b4
wren_a
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|libraries|megafunctions|lpm_mux.inc
1107574776
..|libraries|megafunctions|lpm_decode.inc
1107574570
..|libraries|megafunctions|altsyncram.inc
1107573506
..|libraries|megafunctions|a_rdenreg.inc
1107572148
..|libraries|megafunctions|altrom.inc
1107573422
..|libraries|megafunctions|altram.inc
1107573384
..|libraries|megafunctions|altdpram.inc
1107573082
..|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
decode_9oa
# case_insensitive
# source_file
db|decode_9oa.tdf
1194058559
6
# storage
db|test.(57).cnf
db|test.(57).cnf
# used_port {
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
mux_mib
# case_insensitive
# source_file
db|mux_mib.tdf
1194338544
6
# storage
db|test.(58).cnf
db|test.(58).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data30
data31
data32
data33
data34
data35
data36
data37
data38
data39
sel0
sel1
sel2
result0
result1
result2
result3
result4
}
# end
# entity
sld_offload_buffer_mgr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|libraries|megafunctions|sld_acquisition_buffer.vhd
1114012240
4
# storage
db|test.(59).cnf
db|test.(59).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
buffer_depth
32768
PARAMETER_DEC
USR
mem_address_bits
15
PARAMETER_DEC
USR
data_bits
5
PARAMETER_DEC
USR
data_bit_cntr_bits
3
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
..|libraries|megafunctions|lpm_counter.tdf
1114012448
6
# storage
db|test.(60).cnf
db|test.(60).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
5
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_c58
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
q0
q1
q2
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|lpm_decode.inc
1107574570
..|libraries|megafunctions|dffeea.inc
1107574164
..|libraries|megafunctions|lpm_constant.inc
1107574524
..|libraries|megafunctions|lpm_add_sub.inc
1107574408
..|libraries|megafunctions|cmpconst.inc
1107573980
..|libraries|megafunctions|lpm_compare.inc
1107574500
..|libraries|megafunctions|lpm_counter.inc
1107574548
..|libraries|megafunctions|alt_synch_counter.inc
1107572664
..|libraries|megafunctions|alt_synch_counter_f.inc
1107572680
..|libraries|megafunctions|alt_counter_f10ke.inc
1107572320
..|libraries|megafunctions|alt_counter_stratix.inc
1107572334
}
# end
# entity
cntr_c58
# case_insensitive
# source_file
db|cntr_c58.tdf
1193558640
6
# storage
db|test.(61).cnf
db|test.(61).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
..|libraries|megafunctions|lpm_counter.tdf
1114012448
6
# storage
db|test.(62).cnf
db|test.(62).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
15
PARAMETER_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
32768
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_718
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
q0
q10
q11
q12
q13
q14
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|lpm_decode.inc
1107574570
..|libraries|megafunctions|dffeea.inc
1107574164
..|libraries|megafunctions|lpm_constant.inc
1107574524
..|libraries|megafunctions|lpm_add_sub.inc
1107574408
..|libraries|megafunctions|cmpconst.inc
1107573980
..|libraries|megafunctions|lpm_compare.inc
1107574500
..|libraries|megafunctions|lpm_counter.inc
1107574548
..|libraries|megafunctions|alt_synch_counter.inc
1107572664
..|libraries|megafunctions|alt_synch_counter_f.inc
1107572680
..|libraries|megafunctions|alt_counter_f10ke.inc
1107572320
..|libraries|megafunctions|alt_counter_stratix.inc
1107572334
}
# end
# entity
cntr_718
# case_insensitive
# source_file
db|cntr_718.tdf
1194058561
6
# storage
db|test.(63).cnf
db|test.(63).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
q13
q14
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
..|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|test.(64).cnf
db|test.(64).cnf
# user_parameter {
LPM_WIDTH
5
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data1
data2
data3
data4
enable
load
shiftin
shiftout
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|dffeea.inc
1107574164
..|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
..|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|test.(65).cnf
db|test.(65).cnf
# user_parameter {
LPM_WIDTH
31
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data1
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data2
data30
data3
data4
data5
data6
data7
data8
data9
enable
load
shiftin
shiftout
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|dffeea.inc
1107574164
..|libraries|megafunctions|lpm_constant.inc
1107574524
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive