test.hif

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

Version 5.0 Build 148 04/26/2005 SJ Full Version
10
731
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
mux_2_1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mux_2_1.v
1193478344
7
# storage
db|test.(1).cnf
db|test.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mux_2_1:inst16
mux_2_1:inst20
}
# end
# entity
initial_block
# case_insensitive
# source_file
initial_block.bdf
1193709003
23
# storage
db|test.(2).cnf
db|test.(2).cnf
# hierarchies {
initial_block:inst9
}
# end
# entity
get_response
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
get_response.v
1194340439
7
# storage
db|test.(3).cnf
db|test.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
len1
48
PARAMETER_UNKNOWN
USR
len2
136
PARAMETER_UNKNOWN
USR
pulsewide
1
PARAMETER_UNKNOWN
USR
}
# hierarchies {
initial_block:inst9|get_response:inst3
}
# end
# entity
confirmpulse
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
confirmpulse.v
1192067906
7
# storage
db|test.(4).cnf
db|test.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
initial_block:inst9|get_response:inst3|confirmpulse:pulse_gen
initial_block:inst9|confirmpulse:inst1
confirmpulse:inst18
}
# end
# entity
send_cmd
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
send_cmd.v
1194340469
7
# storage
db|test.(5).cnf
db|test.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
len
48
PARAMETER_UNKNOWN
USR
}
# hierarchies {
initial_block:inst9|send_cmd:inst4
}
# end
# entity
odd_division
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
odd_division.v
1192074804
7
# storage
db|test.(6).cnf
db|test.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
initial_block:inst9|odd_division:clk_50m_25m
odd_division:clk_50m_5m
odd_division:clk_50m_25m
}
# end
# entity
timer
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
timer.v
1192001972
7
# storage
db|test.(7).cnf
db|test.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
initial_block:inst9|timer:inst
initial_block:inst9|timer:delay_250ms
}
# end
# entity
crc8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
crc8.vhd
1193644563
4
# storage
db|test.(8).cnf
db|test.(8).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
initial_block:inst9|crc8:inst10
crc8:inst3
}
# end
# entity
shift_r1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
shift_r1.v
1193551216
7
# storage
db|test.(9).cnf
db|test.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
len1
48
PARAMETER_UNKNOWN
USR
len2
136
PARAMETER_UNKNOWN
USR
}
# hierarchies {
initial_block:inst9|shift_r1:inst5
}
# end
# entity
shift_reg
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
shift_reg.v
1191838800
7
# storage
db|test.(10).cnf
db|test.(10).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
len
48
PARAMETER_UNKNOWN
USR
}
# hierarchies {
initial_block:inst9|shift_reg:inst7
}
# end
# entity
bidirec
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
bidirec.v
1192075256
7
# storage
db|test.(11).cnf
db|test.(11).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
bidirec:inst13
}
# end
# entity
sd_control
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sd_control.v
1194095802
7
# storage
db|test.(12).cnf
db|test.(12).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ram_wide
7
PARAMETER_UNKNOWN
USR
sd_data_wide
4
PARAMETER_UNKNOWN
USR
sd_ad_wide
32
PARAMETER_UNKNOWN
USR
cmd_1_en
1
PARAMETER_UNKNOWN
USR
}
# hierarchies {
sd_control:inst
}
# end
# entity
shift_reg
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
shift_reg.v
1191838800
7
# storage
db|test.(13).cnf
db|test.(13).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
len
48
PARAMETER_DEC
DEF
}
# hierarchies {
sd_control:inst|shift_reg:cmd18
}
# end
# entity
fifo_control
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fifo_control.v
1194072557
7
# storage
db|test.(14).cnf
db|test.(14).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
wd
32
PARAMETER_UNKNOWN
USR
}
# hierarchies {
fifo_control:inst26
}
# end
# entity
mux_2bus
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mux_2bus.v
1193718034
7
# storage
db|test.(15).cnf
db|test.(15).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mux_2bus:inst10
}
# end
# entity
lpm_mux
# case_insensitive
# source_file
..|libraries|megafunctions|lpm_mux.tdf
1114012454
6
# storage
db|test.(16).cnf
db|test.(16).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
32
PARAMETER_DEC
USR
LPM_SIZE
2
PARAMETER_DEC
USR
LPM_WIDTHS
1
PARAMETER_DEC
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_9oc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
}
# used_port {
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
data
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
sel
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|muxlut.inc
1107575250
..|libraries|megafunctions|bypassff.inc
1107573920
..|libraries|megafunctions|altshift.inc
1107573438
}
# hierarchies {
mux_2bus:inst10|lpm_mux:lpm_mux_component
}
# end
# entity
mux_9oc
# case_insensitive
# source_file
db|mux_9oc.tdf
1193718076
6
# storage
db|test.(17).cnf
db|test.(17).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data30
data31
data32
data33
data34
data35
data36
data37
data38
data39
data40
data41
data42
data43
data44
data45
data46
data47
data48
data49
data50
data51
data52
data53
data54
data55
data56
data57
data58
data59
data60
data61
data62
data63
sel0
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
result16
result17
result18
result19
result20
result21
result22
result23
result24
result25
result26
result27
result28
result29
result30
result31
}
# hierarchies {
mux_2bus:inst10|lpm_mux:lpm_mux_component|mux_9oc:auto_generated
}
# end
# entity
ram_4_32
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ram_4_32.v
1193904300
7
# storage
db|test.(18).cnf
db|test.(18).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
ram_4_32:inst24
ram_4_32:inst1
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|test.(19).cnf
db|test.(19).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
4
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
4
PARAMETER_DEC
USR
NUMWORDS_B
16
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
test.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_c9h1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
clock0
clock1
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
rden_b
wren_a
}
# include_file {
..|libraries|megafunctions|aglobal50.inc
1114012420
..|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|libraries|megafunctions|lpm_mux.inc
1107574776
..|libraries|megafunctions|lpm_decode.inc
1107574570
..|libraries|megafunctions|altsyncram.inc
1107573506
..|libraries|megafunctions|a_rdenreg.inc
1107572148
..|libraries|megafunctions|altrom.inc
1107573422
..|libraries|megafunctions|altram.inc
1107573384
..|libraries|megafunctions|altdpram.inc
1107573082
..|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
ram_4_32:inst24|altsyncram:altsyncram_component
ram_4_32:inst1|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_c9h1
# case_insensitive
# source_file
db|altsyncram_c9h1.tdf
1193904511
6
# storage
db|test.(20).cnf
db|test.(20).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_b0
address_b1
address_b2
address_b3
clock0
clock1
rden_b
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17