mux_eib.tdf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=5 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


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--synthesis_resources = lut 5 
SUBDESIGN mux_eib
( 
	data[9..0]	:	input;
	result[4..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[4..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data110w[1..0]	: WIRE;
	w_data122w[1..0]	: WIRE;
	w_data134w[1..0]	: WIRE;
	w_data146w[1..0]	: WIRE;
	w_data96w[1..0]	: WIRE;
	w_result103w	: WIRE;
	w_result111w	: WIRE;
	w_result117w	: WIRE;
	w_result123w	: WIRE;
	w_result129w	: WIRE;
	w_result135w	: WIRE;
	w_result141w	: WIRE;
	w_result147w	: WIRE;
	w_result153w	: WIRE;
	w_result97w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result147w, w_result135w, w_result123w, w_result111w, w_result97w);
	sel_node[] = ( sel[0..0]);
	w_data110w[] = ( data[6..6], data[1..1]);
	w_data122w[] = ( data[7..7], data[2..2]);
	w_data134w[] = ( data[8..8], data[3..3]);
	w_data146w[] = ( data[9..9], data[4..4]);
	w_data96w[] = ( data[5..5], data[0..0]);
	w_result103w = ((sel_node[] & w_data96w[1..1]) # ((! sel_node[]) & w_data96w[0..0]));
	w_result111w = w_result117w;
	w_result117w = ((sel_node[] & w_data110w[1..1]) # ((! sel_node[]) & w_data110w[0..0]));
	w_result123w = w_result129w;
	w_result129w = ((sel_node[] & w_data122w[1..1]) # ((! sel_node[]) & w_data122w[0..0]));
	w_result135w = w_result141w;
	w_result141w = ((sel_node[] & w_data134w[1..1]) # ((! sel_node[]) & w_data134w[0..0]));
	w_result147w = w_result153w;
	w_result153w = ((sel_node[] & w_data146w[1..1]) # ((! sel_node[]) & w_data146w[0..0]));
	w_result97w = w_result103w;
END;
--VALID FILE