mux_iib.tdf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=4 LPM_WIDTH=6 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = lut 12 
SUBDESIGN mux_iib
( 
	data[23..0]	:	input;
	result[5..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[5..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data249w[3..0]	: WIRE;
	w_data279w[3..0]	: WIRE;
	w_data304w[3..0]	: WIRE;
	w_data329w[3..0]	: WIRE;
	w_data354w[3..0]	: WIRE;
	w_data379w[3..0]	: WIRE;
	w_result250w	: WIRE;
	w_result260w	: WIRE;
	w_result261w	: WIRE;
	w_result280w	: WIRE;
	w_result290w	: WIRE;
	w_result291w	: WIRE;
	w_result305w	: WIRE;
	w_result315w	: WIRE;
	w_result316w	: WIRE;
	w_result330w	: WIRE;
	w_result340w	: WIRE;
	w_result341w	: WIRE;
	w_result355w	: WIRE;
	w_result365w	: WIRE;
	w_result366w	: WIRE;
	w_result380w	: WIRE;
	w_result390w	: WIRE;
	w_result391w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result380w, w_result355w, w_result330w, w_result305w, w_result280w, w_result250w);
	sel_node[] = ( sel[1..0]);
	w_data249w[] = ( data[18..18], data[12..12], data[6..6], data[0..0]);
	w_data279w[] = ( data[19..19], data[13..13], data[7..7], data[1..1]);
	w_data304w[] = ( data[20..20], data[14..14], data[8..8], data[2..2]);
	w_data329w[] = ( data[21..21], data[15..15], data[9..9], data[3..3]);
	w_data354w[] = ( data[22..22], data[16..16], data[10..10], data[4..4]);
	w_data379w[] = ( data[23..23], data[17..17], data[11..11], data[5..5]);
	w_result250w = w_result260w;
	w_result260w = (((w_data249w[1..1] & sel_node[0..0]) & (! w_result261w)) # (w_result261w & (w_data249w[3..3] # (! sel_node[0..0]))));
	w_result261w = (((w_data249w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data249w[2..2])));
	w_result280w = w_result290w;
	w_result290w = (((w_data279w[1..1] & sel_node[0..0]) & (! w_result291w)) # (w_result291w & (w_data279w[3..3] # (! sel_node[0..0]))));
	w_result291w = (((w_data279w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data279w[2..2])));
	w_result305w = w_result315w;
	w_result315w = (((w_data304w[1..1] & sel_node[0..0]) & (! w_result316w)) # (w_result316w & (w_data304w[3..3] # (! sel_node[0..0]))));
	w_result316w = (((w_data304w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data304w[2..2])));
	w_result330w = w_result340w;
	w_result340w = (((w_data329w[1..1] & sel_node[0..0]) & (! w_result341w)) # (w_result341w & (w_data329w[3..3] # (! sel_node[0..0]))));
	w_result341w = (((w_data329w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data329w[2..2])));
	w_result355w = w_result365w;
	w_result365w = (((w_data354w[1..1] & sel_node[0..0]) & (! w_result366w)) # (w_result366w & (w_data354w[3..3] # (! sel_node[0..0]))));
	w_result366w = (((w_data354w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data354w[2..2])));
	w_result380w = w_result390w;
	w_result390w = (((w_data379w[1..1] & sel_node[0..0]) & (! w_result391w)) # (w_result391w & (w_data379w[3..3] # (! sel_node[0..0]))));
	w_result391w = (((w_data379w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data379w[2..2])));
END;
--VALID FILE