test.tan.qmsg

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "sd_control:inst\|ram_address\[2\] sd_control:inst\|mm sd_clk_in 79 ps " "Info: Found hold time violation between source  pin or register \"sd_control:inst\|ram_address\[2\]\" and destination pin or register \"sd_control:inst\|mm\" for clock \"sd_clk_in\" (Hold time is 79 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.614 ns + Largest " "Info: + Largest clock skew is 5.614 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sd_clk_in destination 13.603 ns + Longest register " "Info: + Longest clock path from clock \"sd_clk_in\" to destination register is 13.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns sd_clk_in 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'sd_clk_in'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { sd_clk_in } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 56 40 208 72 "sd_clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.232 ns sd_clk_in~clkctrl 2 COMB CLKCTRL_G10 18 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.232 ns; Loc. = CLKCTRL_G10; Fanout = 18; COMB Node = 'sd_clk_in~clkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.132 ns" { sd_clk_in sd_clk_in~clkctrl } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 56 40 208 72 "sd_clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.989 ns) 3.434 ns initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd 3 REG LCFF_X50_Y33_N31 3 " "Info: 3: + IC(1.213 ns) + CELL(0.989 ns) = 3.434 ns; Loc. = LCFF_X50_Y33_N31; Fanout = 3; REG Node = 'initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.202 ns" { sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd } "NODE_NAME" } "" } } { "odd_division.v" "" { Text "C:/altera/quartus50/workone/odd_division.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.989 ns) + CELL(0.000 ns) 5.423 ns initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd~clkctrl 4 COMB CLKCTRL_G9 801 " "Info: 4: + IC(1.989 ns) + CELL(0.000 ns) = 5.423 ns; Loc. = CLKCTRL_G9; Fanout = 801; COMB Node = 'initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd~clkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.989 ns" { initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl } "NODE_NAME" } "" } } { "odd_division.v" "" { Text "C:/altera/quartus50/workone/odd_division.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.203 ns) + CELL(0.989 ns) 7.615 ns initial_block:inst9\|get_response:inst3\|initial_done 5 REG LCFF_X47_Y29_N13 98 " "Info: 5: + IC(1.203 ns) + CELL(0.989 ns) = 7.615 ns; Loc. = LCFF_X47_Y29_N13; Fanout = 98; REG Node = 'initial_block:inst9\|get_response:inst3\|initial_done'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.192 ns" { initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done } "NODE_NAME" } "" } } { "get_response.v" "" { Text "C:/altera/quartus50/workone/get_response.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.531 ns) + CELL(0.378 ns) 9.524 ns mux_2_1:inst16\|out~8 6 COMB LCCOMB_X50_Y33_N0 2 " "Info: 6: + IC(1.531 ns) + CELL(0.378 ns) = 9.524 ns; Loc. = LCCOMB_X50_Y33_N0; Fanout = 2; COMB Node = 'mux_2_1:inst16\|out~8'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.909 ns" { initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 } "NODE_NAME" } "" } } { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.206 ns) + CELL(0.000 ns) 11.730 ns mux_2_1:inst16\|out~8clkctrl 7 COMB CLKCTRL_G8 951 " "Info: 7: + IC(2.206 ns) + CELL(0.000 ns) = 11.730 ns; Loc. = CLKCTRL_G8; Fanout = 951; COMB Node = 'mux_2_1:inst16\|out~8clkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.206 ns" { mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl } "NODE_NAME" } "" } } { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.679 ns) 13.603 ns sd_control:inst\|mm 8 REG LCFF_X45_Y28_N5 4 " "Info: 8: + IC(1.194 ns) + CELL(0.679 ns) = 13.603 ns; Loc. = LCFF_X45_Y28_N5; Fanout = 4; REG Node = 'sd_control:inst\|mm'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.873 ns" { mux_2_1:inst16|out~8clkctrl sd_control:inst|mm } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.135 ns 30.40 % " "Info: Total cell delay = 4.135 ns ( 30.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.468 ns 69.60 % " "Info: Total interconnect delay = 9.468 ns ( 69.60 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "13.603 ns" { sd_clk_in sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|mm } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.603 ns" { sd_clk_in sd_clk_in~combout sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|mm } { 0.0ns 0.0ns 0.132ns 1.213ns 1.989ns 1.203ns 1.531ns 2.206ns 1.194ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.378ns 0.0ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sd_clk_in source 7.989 ns - Shortest register " "Info: - Shortest clock path from clock \"sd_clk_in\" to source register is 7.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns sd_clk_in 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'sd_clk_in'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { sd_clk_in } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 56 40 208 72 "sd_clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.146 ns) + CELL(0.664 ns) 3.910 ns mux_2_1:inst16\|out~8 2 COMB LCCOMB_X50_Y33_N0 2 " "Info: 2: + IC(2.146 ns) + CELL(0.664 ns) = 3.910 ns; Loc. = LCCOMB_X50_Y33_N0; Fanout = 2; COMB Node = 'mux_2_1:inst16\|out~8'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.810 ns" { sd_clk_in mux_2_1:inst16|out~8 } "NODE_NAME" } "" } } { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.206 ns) + CELL(0.000 ns) 6.116 ns mux_2_1:inst16\|out~8clkctrl 3 COMB CLKCTRL_G8 951 " "Info: 3: + IC(2.206 ns) + CELL(0.000 ns) = 6.116 ns; Loc. = CLKCTRL_G8; Fanout = 951; COMB Node = 'mux_2_1:inst16\|out~8clkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.206 ns" { mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl } "NODE_NAME" } "" } } { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.679 ns) 7.989 ns sd_control:inst\|ram_address\[2\] 4 REG LCFF_X51_Y29_N9 5 " "Info: 4: + IC(1.194 ns) + CELL(0.679 ns) = 7.989 ns; Loc. = LCFF_X51_Y29_N9; Fanout = 5; REG Node = 'sd_control:inst\|ram_address\[2\]'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.873 ns" { mux_2_1:inst16|out~8clkctrl sd_control:inst|ram_address[2] } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.443 ns 30.58 % " "Info: Total cell delay = 2.443 ns ( 30.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.546 ns 69.42 % " "Info: Total interconnect delay = 5.546 ns ( 69.42 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "7.989 ns" { sd_clk_in mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|ram_address[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.989 ns" { sd_clk_in sd_clk_in~combout mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|ram_address[2] } { 0.0ns 0.0ns 2.146ns 2.206ns 1.194ns } { 0.0ns 1.1ns 0.664ns 0.0ns 0.679ns } } }  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "13.603 ns" { sd_clk_in sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|mm } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.603 ns" { sd_clk_in sd_clk_in~combout sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|mm } { 0.0ns 0.0ns 0.132ns 1.213ns 1.989ns 1.203ns 1.531ns 2.206ns 1.194ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.378ns 0.0ns 0.679ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "7.989 ns" { sd_clk_in mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|ram_address[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.989 ns" { sd_clk_in sd_clk_in~combout mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|ram_address[2] } { 0.0ns 0.0ns 2.146ns 2.206ns 1.194ns } { 0.0ns 1.1ns 0.664ns 0.0ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns - " "Info: - Micro clock to output delay of source is 0.310 ns" {  } { { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 40 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.436 ns - Shortest register register " "Info: - Shortest register to register delay is 5.436 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sd_control:inst\|ram_address\[2\] 1 REG LCFF_X51_Y29_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X51_Y29_N9; Fanout = 5; REG Node = 'sd_control:inst\|ram_address\[2\]'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { sd_control:inst|ram_address[2] } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.145 ns) + CELL(0.378 ns) 1.523 ns sd_control:inst\|reduce_nor~398 2 COMB LCCOMB_X47_Y29_N6 1 " "Info: 2: + IC(1.145 ns) + CELL(0.378 ns) = 1.523 ns; Loc. = LCCOMB_X47_Y29_N6; Fanout = 1; COMB Node = 'sd_control:inst\|reduce_nor~398'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.523 ns" { sd_control:inst|ram_address[2] sd_control:inst|reduce_nor~398 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.210 ns) 2.117 ns sd_control:inst\|reduce_nor~1 3 COMB LCCOMB_X47_Y29_N4 5 " "Info: 3: + IC(0.384 ns) + CELL(0.210 ns) = 2.117 ns; Loc. = LCCOMB_X47_Y29_N4; Fanout = 5; COMB Node = 'sd_control:inst\|reduce_nor~1'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.594 ns" { sd_control:inst|reduce_nor~398 sd_control:inst|reduce_nor~1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.378 ns) 2.854 ns sd_control:inst\|always2~3 4 COMB LCCOMB_X47_Y29_N16 35 " "Info: 4: + IC(0.359 ns) + CELL(0.378 ns) = 2.854 ns; Loc. = LCCOMB_X47_Y29_N16; Fanout = 35; COMB Node = 'sd_control:inst\|always2~3'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.737 ns" { sd_control:inst|reduce_nor~1 sd_control:inst|always2~3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.836 ns) + CELL(0.636 ns) 5.326 ns sd_control:inst\|mm~86 5 COMB LCCOMB_X45_Y28_N4 1 " "Info: 5: + IC(1.836 ns) + CELL(0.636 ns) = 5.326 ns; Loc. = LCCOMB_X45_Y28_N4; Fanout = 1; COMB Node = 'sd_control:inst\|mm~86'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.472 ns" { sd_control:inst|always2~3 sd_control:inst|mm~86 } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 5.436 ns sd_control:inst\|mm 6 REG LCFF_X45_Y28_N5 4 " "Info: 6: + IC(0.000 ns) + CELL(0.110 ns) = 5.436 ns; Loc. = LCFF_X45_Y28_N5; Fanout = 4; REG Node = 'sd_control:inst\|mm'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.110 ns" { sd_control:inst|mm~86 sd_control:inst|mm } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.712 ns 31.49 % " "Info: Total cell delay = 1.712 ns ( 31.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.724 ns 68.51 % " "Info: Total interconnect delay = 3.724 ns ( 68.51 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "5.436 ns" { sd_control:inst|ram_address[2] sd_control:inst|reduce_nor~398 sd_control:inst|reduce_nor~1 sd_control:inst|always2~3 sd_control:inst|mm~86 sd_control:inst|mm } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.436 ns" { sd_control:inst|ram_address[2] sd_control:inst|reduce_nor~398 sd_control:inst|reduce_nor~1 sd_control:inst|always2~3 sd_control:inst|mm~86 sd_control:inst|mm } { 0.0ns 1.145ns 0.384ns 0.359ns 1.836ns 0.0ns } { 0.0ns 0.378ns 0.21ns 0.378ns 0.636ns 0.11ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.211 ns + " "Info: + Micro hold delay of destination is 0.211 ns" {  } { { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 53 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 40 -1 0 } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 53 -1 0 } }  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "13.603 ns" { sd_clk_in sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|mm } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.603 ns" { sd_clk_in sd_clk_in~combout sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|mm } { 0.0ns 0.0ns 0.132ns 1.213ns 1.989ns 1.203ns 1.531ns 2.206ns 1.194ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.378ns 0.0ns 0.679ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "7.989 ns" { sd_clk_in mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|ram_address[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.989 ns" { sd_clk_in sd_clk_in~combout mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|ram_address[2] } { 0.0ns 0.0ns 2.146ns 2.206ns 1.194ns } { 0.0ns 1.1ns 0.664ns 0.0ns 0.679ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "5.436 ns" { sd_control:inst|ram_address[2] sd_control:inst|reduce_nor~398 sd_control:inst|reduce_nor~1 sd_control:inst|always2~3 sd_control:inst|mm~86 sd_control:inst|mm } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.436 ns" { sd_control:inst|ram_address[2] sd_control:inst|reduce_nor~398 sd_control:inst|reduce_nor~1 sd_control:inst|always2~3 sd_control:inst|mm~86 sd_control:inst|mm } { 0.0ns 1.145ns 0.384ns 0.359ns 1.836ns 0.0ns } { 0.0ns 0.378ns 0.21ns 0.378ns 0.636ns 0.11ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "initial_block:inst9\|get_response:inst3\|data136\[22\] vp sd_clk_in 6.017 ns register " "Info: tsu for register \"initial_block:inst9\|get_response:inst3\|data136\[22\]\" (data pin = \"vp\", clock pin = \"sd_clk_in\") is 6.017 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.371 ns + Longest pin register " "Info: + Longest pin to register delay is 13.371 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns vp 1 PIN PIN_E15 469 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_E15; Fanout = 469; PIN Node = 'vp'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { vp } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 360 40 208 376 "vp" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.829 ns) + CELL(0.378 ns) 9.141 ns initial_block:inst9\|get_response:inst3\|data48\[34\]~2888 2 COMB LCCOMB_X35_Y16_N22 2 " "Info: 2: + IC(7.829 ns) + CELL(0.378 ns) = 9.141 ns; Loc. = LCCOMB_X35_Y16_N22; Fanout = 2; COMB Node = 'initial_block:inst9\|get_response:inst3\|data48\[34\]~2888'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "8.207 ns" { vp initial_block:inst9|get_response:inst3|data48[34]~2888 } "NODE_NAME" } "" } } { "get_response.v" "" { Text "C:/altera/quartus50/workone/get_response.v" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.636 ns) 10.160 ns initial_block:inst9\|get_response:inst3\|data136\[101\]~3486 3 COMB LCCOMB_X35_Y