test.tan.qmsg

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\] register sld_hub:sld_hub_inst\|hub_tdo 79.99 MHz 12.502 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 79.99 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 12.502 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.983 ns + Longest register register " "Info: + Longest register to register delay is 5.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\] 1 REG LCFF_X16_Y21_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y21_N21; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\]'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.654 ns) + CELL(0.664 ns) 2.318 ns sld_hub:sld_hub_inst\|hub_tdo~351 2 COMB LCCOMB_X15_Y22_N0 1 " "Info: 2: + IC(1.654 ns) + CELL(0.664 ns) = 2.318 ns; Loc. = LCCOMB_X15_Y22_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~351'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.318 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~351 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.134 ns) + CELL(0.664 ns) 4.116 ns sld_hub:sld_hub_inst\|hub_tdo~354 3 COMB LCCOMB_X15_Y21_N10 1 " "Info: 3: + IC(1.134 ns) + CELL(0.664 ns) = 4.116 ns; Loc. = LCCOMB_X15_Y21_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~354'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.798 ns" { sld_hub:sld_hub_inst|hub_tdo~351 sld_hub:sld_hub_inst|hub_tdo~354 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(0.664 ns) 5.873 ns sld_hub:sld_hub_inst\|hub_tdo~356 4 COMB LCCOMB_X12_Y21_N20 1 " "Info: 4: + IC(1.093 ns) + CELL(0.664 ns) = 5.873 ns; Loc. = LCCOMB_X12_Y21_N20; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~356'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.757 ns" { sld_hub:sld_hub_inst|hub_tdo~354 sld_hub:sld_hub_inst|hub_tdo~356 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 5.983 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LCFF_X12_Y21_N21 1 " "Info: 5: + IC(0.000 ns) + CELL(0.110 ns) = 5.983 ns; Loc. = LCFF_X12_Y21_N21; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.110 ns" { sld_hub:sld_hub_inst|hub_tdo~356 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.102 ns 35.13 % " "Info: Total cell delay = 2.102 ns ( 35.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.881 ns 64.87 % " "Info: Total interconnect delay = 3.881 ns ( 64.87 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "5.983 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~351 sld_hub:sld_hub_inst|hub_tdo~354 sld_hub:sld_hub_inst|hub_tdo~356 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.983 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~351 sld_hub:sld_hub_inst|hub_tdo~354 sld_hub:sld_hub_inst|hub_tdo~356 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.654ns 1.134ns 1.093ns 0.000ns } { 0.000ns 0.664ns 0.664ns 0.664ns 0.110ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 1.908 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 1.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 620 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 620; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.229 ns) + CELL(0.679 ns) 1.908 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X12_Y21_N21 1 " "Info: 3: + IC(1.229 ns) + CELL(0.679 ns) = 1.908 ns; Loc. = LCFF_X12_Y21_N21; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.908 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.59 % " "Info: Total cell delay = 0.679 ns ( 35.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.229 ns 64.41 % " "Info: Total interconnect delay = 1.229 ns ( 64.41 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.908 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.908 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.229ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 1.906 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 1.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 620 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 620; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.227 ns) + CELL(0.679 ns) 1.906 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\] 3 REG LCFF_X16_Y21_N21 2 " "Info: 3: + IC(1.227 ns) + CELL(0.679 ns) = 1.906 ns; Loc. = LCFF_X16_Y21_N21; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\]'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.906 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.62 % " "Info: Total cell delay = 0.679 ns ( 35.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.227 ns 64.38 % " "Info: Total interconnect delay = 1.227 ns ( 64.38 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } { 0.000ns 0.000ns 1.227ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.908 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.908 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.229ns } { 0.000ns 0.000ns 0.679ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } { 0.000ns 0.000ns 1.227ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "5.983 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~351 sld_hub:sld_hub_inst|hub_tdo~354 sld_hub:sld_hub_inst|hub_tdo~356 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.983 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~351 sld_hub:sld_hub_inst|hub_tdo~354 sld_hub:sld_hub_inst|hub_tdo~356 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.654ns 1.134ns 1.093ns 0.000ns } { 0.000ns 0.664ns 0.664ns 0.664ns 0.110ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.908 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.908 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.229ns } { 0.000ns 0.000ns 0.679ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } { 0.000ns 0.000ns 1.227ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "sd_clk_in 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"sd_clk_in\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}