test.tan.qmsg

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "odd_division:clk_50m_5m\|clk_odd " "Info: Detected ripple clock \"odd_division:clk_50m_5m\|clk_odd\" as buffer" {  } { { "odd_division.v" "" { Text "C:/altera/quartus50/workone/odd_division.v" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "odd_division:clk_50m_5m\|clk_odd" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mux_2_1:inst16\|out~8 " "Info: Detected gated clock \"mux_2_1:inst16\|out~8\" as buffer" {  } { { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mux_2_1:inst16\|out~8" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "initial_block:inst9\|shift_r1:inst5\|flag " "Info: Detected ripple clock \"initial_block:inst9\|shift_r1:inst5\|flag\" as buffer" {  } { { "shift_r1.v" "" { Text "C:/altera/quartus50/workone/shift_r1.v" 20 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "initial_block:inst9\|shift_r1:inst5\|flag" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "initial_block:inst9\|send_cmd:inst4\|crcflag " "Info: Detected ripple clock \"initial_block:inst9\|send_cmd:inst4\|crcflag\" as buffer" {  } { { "send_cmd.v" "" { Text "C:/altera/quartus50/workone/send_cmd.v" 34 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "initial_block:inst9\|send_cmd:inst4\|crcflag" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "initial_block:inst9\|get_response:inst3\|initial_done " "Info: Detected ripple clock \"initial_block:inst9\|get_response:inst3\|initial_done\" as buffer" {  } { { "get_response.v" "" { Text "C:/altera/quartus50/workone/get_response.v" 30 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "initial_block:inst9\|get_response:inst3\|initial_done" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd " "Info: Detected ripple clock \"initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd\" as buffer" {  } { { "odd_division.v" "" { Text "C:/altera/quartus50/workone/odd_division.v" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sd_clk_in register sd_control:inst\|block_num\[9\]~reg0 register sd_control:inst\|cmd\[43\] 36.62 MHz 27.306 ns Internal " "Info: Clock \"sd_clk_in\" has Internal fmax of 36.62 MHz between source register \"sd_control:inst\|block_num\[9\]~reg0\" and destination register \"sd_control:inst\|cmd\[43\]\" (period= 27.306 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.761 ns + Longest register register " "Info: + Longest register to register delay is 7.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sd_control:inst\|block_num\[9\]~reg0 1 REG LCFF_X46_Y29_N19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X46_Y29_N19; Fanout = 3; REG Node = 'sd_control:inst\|block_num\[9\]~reg0'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { sd_control:inst|block_num[9]~reg0 } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 142 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.964 ns) + CELL(0.664 ns) 2.628 ns sd_control:inst\|reduce_nor~402 2 COMB LCCOMB_X47_Y29_N28 1 " "Info: 2: + IC(1.964 ns) + CELL(0.664 ns) = 2.628 ns; Loc. = LCCOMB_X47_Y29_N28; Fanout = 1; COMB Node = 'sd_control:inst\|reduce_nor~402'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.628 ns" { sd_control:inst|block_num[9]~reg0 sd_control:inst|reduce_nor~402 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.636 ns) 3.692 ns sd_control:inst\|reduce_nor~404 3 COMB LCCOMB_X47_Y29_N22 2 " "Info: 3: + IC(0.428 ns) + CELL(0.636 ns) = 3.692 ns; Loc. = LCCOMB_X47_Y29_N22; Fanout = 2; COMB Node = 'sd_control:inst\|reduce_nor~404'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.064 ns" { sd_control:inst|reduce_nor~402 sd_control:inst|reduce_nor~404 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.379 ns) + CELL(0.636 ns) 4.707 ns sd_control:inst\|always2~3 4 COMB LCCOMB_X47_Y29_N16 35 " "Info: 4: + IC(0.379 ns) + CELL(0.636 ns) = 4.707 ns; Loc. = LCCOMB_X47_Y29_N16; Fanout = 35; COMB Node = 'sd_control:inst\|always2~3'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.015 ns" { sd_control:inst|reduce_nor~404 sd_control:inst|always2~3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.378 ns) 5.451 ns sd_control:inst\|cmd\[44\]~778 5 COMB LCCOMB_X47_Y29_N30 32 " "Info: 5: + IC(0.366 ns) + CELL(0.378 ns) = 5.451 ns; Loc. = LCCOMB_X47_Y29_N30; Fanout = 32; COMB Node = 'sd_control:inst\|cmd\[44\]~778'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.744 ns" { sd_control:inst|always2~3 sd_control:inst|cmd[44]~778 } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.438 ns) + CELL(0.872 ns) 7.761 ns sd_control:inst\|cmd\[43\] 6 REG LCFF_X45_Y28_N13 2 " "Info: 6: + IC(1.438 ns) + CELL(0.872 ns) = 7.761 ns; Loc. = LCFF_X45_Y28_N13; Fanout = 2; REG Node = 'sd_control:inst\|cmd\[43\]'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.310 ns" { sd_control:inst|cmd[44]~778 sd_control:inst|cmd[43] } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 45 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.186 ns 41.05 % " "Info: Total cell delay = 3.186 ns ( 41.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.575 ns 58.95 % " "Info: Total interconnect delay = 4.575 ns ( 58.95 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "7.761 ns" { sd_control:inst|block_num[9]~reg0 sd_control:inst|reduce_nor~402 sd_control:inst|reduce_nor~404 sd_control:inst|always2~3 sd_control:inst|cmd[44]~778 sd_control:inst|cmd[43] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.761 ns" { sd_control:inst|block_num[9]~reg0 sd_control:inst|reduce_nor~402 sd_control:inst|reduce_nor~404 sd_control:inst|always2~3 sd_control:inst|cmd[44]~778 sd_control:inst|cmd[43] } { 0.000ns 1.964ns 0.428ns 0.379ns 0.366ns 1.438ns } { 0.000ns 0.664ns 0.636ns 0.636ns 0.378ns 0.872ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.622 ns - Smallest " "Info: - Smallest clock skew is -5.622 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sd_clk_in destination 7.989 ns + Shortest register " "Info: + Shortest clock path from clock \"sd_clk_in\" to destination register is 7.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns sd_clk_in 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'sd_clk_in'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { sd_clk_in } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 56 40 208 72 "sd_clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.146 ns) + CELL(0.664 ns) 3.910 ns mux_2_1:inst16\|out~8 2 COMB LCCOMB_X50_Y33_N0 2 " "Info: 2: + IC(2.146 ns) + CELL(0.664 ns) = 3.910 ns; Loc. = LCCOMB_X50_Y33_N0; Fanout = 2; COMB Node = 'mux_2_1:inst16\|out~8'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.810 ns" { sd_clk_in mux_2_1:inst16|out~8 } "NODE_NAME" } "" } } { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.206 ns) + CELL(0.000 ns) 6.116 ns mux_2_1:inst16\|out~8clkctrl 3 COMB CLKCTRL_G8 951 " "Info: 3: + IC(2.206 ns) + CELL(0.000 ns) = 6.116 ns; Loc. = CLKCTRL_G8; Fanout = 951; COMB Node = 'mux_2_1:inst16\|out~8clkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.206 ns" { mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl } "NODE_NAME" } "" } } { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.679 ns) 7.989 ns sd_control:inst\|cmd\[43\] 4 REG LCFF_X45_Y28_N13 2 " "Info: 4: + IC(1.194 ns) + CELL(0.679 ns) = 7.989 ns; Loc. = LCFF_X45_Y28_N13; Fanout = 2; REG Node = 'sd_control:inst\|cmd\[43\]'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.873 ns" { mux_2_1:inst16|out~8clkctrl sd_control:inst|cmd[43] } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 45 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.443 ns 30.58 % " "Info: Total cell delay = 2.443 ns ( 30.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.546 ns 69.42 % " "Info: Total interconnect delay = 5.546 ns ( 69.42 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "7.989 ns" { sd_clk_in mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|cmd[43] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.989 ns" { sd_clk_in sd_clk_in~combout mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|cmd[43] } { 0.000ns 0.000ns 2.146ns 2.206ns 1.194ns } { 0.000ns 1.100ns 0.664ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sd_clk_in source 13.611 ns - Longest register " "Info: - Longest clock path from clock \"sd_clk_in\" to source register is 13.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns sd_clk_in 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'sd_clk_in'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { sd_clk_in } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 56 40 208 72 "sd_clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.232 ns sd_clk_in~clkctrl 2 COMB CLKCTRL_G10 18 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.232 ns; Loc. = CLKCTRL_G10; Fanout = 18; COMB Node = 'sd_clk_in~clkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "0.132 ns" { sd_clk_in sd_clk_in~clkctrl } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 56 40 208 72 "sd_clk_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.989 ns) 3.434 ns initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd 3 REG LCFF_X50_Y33_N31 3 " "Info: 3: + IC(1.213 ns) + CELL(0.989 ns) = 3.434 ns; Loc. = LCFF_X50_Y33_N31; Fanout = 3; REG Node = 'initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.202 ns" { sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd } "NODE_NAME" } "" } } { "odd_division.v" "" { Text "C:/altera/quartus50/workone/odd_division.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.989 ns) + CELL(0.000 ns) 5.423 ns initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd~clkctrl 4 COMB CLKCTRL_G9 801 " "Info: 4: + IC(1.989 ns) + CELL(0.000 ns) = 5.423 ns; Loc. = CLKCTRL_G9; Fanout = 801; COMB Node = 'initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd~clkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.989 ns" { initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl } "NODE_NAME" } "" } } { "odd_division.v" "" { Text "C:/altera/quartus50/workone/odd_division.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.203 ns) + CELL(0.989 ns) 7.615 ns initial_block:inst9\|get_response:inst3\|initial_done 5 REG LCFF_X47_Y29_N13 98 " "Info: 5: + IC(1.203 ns) + CELL(0.989 ns) = 7.615 ns; Loc. = LCFF_X47_Y29_N13; Fanout = 98; REG Node = 'initial_block:inst9\|get_response:inst3\|initial_done'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.192 ns" { initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done } "NODE_NAME" } "" } } { "get_response.v" "" { Text "C:/altera/quartus50/workone/get_response.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.531 ns) + CELL(0.378 ns) 9.524 ns mux_2_1:inst16\|out~8 6 COMB LCCOMB_X50_Y33_N0 2 " "Info: 6: + IC(1.531 ns) + CELL(0.378 ns) = 9.524 ns; Loc. = LCCOMB_X50_Y33_N0; Fanout = 2; COMB Node = 'mux_2_1:inst16\|out~8'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.909 ns" { initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 } "NODE_NAME" } "" } } { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.206 ns) + CELL(0.000 ns) 11.730 ns mux_2_1:inst16\|out~8clkctrl 7 COMB CLKCTRL_G8 951 " "Info: 7: + IC(2.206 ns) + CELL(0.000 ns) = 11.730 ns; Loc. = CLKCTRL_G8; Fanout = 951; COMB Node = 'mux_2_1:inst16\|out~8clkctrl'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "2.206 ns" { mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl } "NODE_NAME" } "" } } { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.202 ns) + CELL(0.679 ns) 13.611 ns sd_control:inst\|block_num\[9\]~reg0 8 REG LCFF_X46_Y29_N19 3 " "Info: 8: + IC(1.202 ns) + CELL(0.679 ns) = 13.611 ns; Loc. = LCFF_X46_Y29_N19; Fanout = 3; REG Node = 'sd_control:inst\|block_num\[9\]~reg0'" {  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "1.881 ns" { mux_2_1:inst16|out~8clkctrl sd_control:inst|block_num[9]~reg0 } "NODE_NAME" } "" } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 142 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.135 ns 30.38 % " "Info: Total cell delay = 4.135 ns ( 30.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.476 ns 69.62 % " "Info: Total interconnect delay = 9.476 ns ( 69.62 % )" {  } {  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "13.611 ns" { sd_clk_in sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|block_num[9]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.611 ns" { sd_clk_in sd_clk_in~combout sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|block_num[9]~reg0 } { 0.000ns 0.000ns 0.132ns 1.213ns 1.989ns 1.203ns 1.531ns 2.206ns 1.202ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.378ns 0.000ns 0.679ns } } }  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "7.989 ns" { sd_clk_in mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|cmd[43] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.989 ns" { sd_clk_in sd_clk_in~combout mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|cmd[43] } { 0.000ns 0.000ns 2.146ns 2.206ns 1.194ns } { 0.000ns 1.100ns 0.664ns 0.000ns 0.679ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "13.611 ns" { sd_clk_in sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|block_num[9]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.611 ns" { sd_clk_in sd_clk_in~combout sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|block_num[9]~reg0 } { 0.000ns 0.000ns 0.132ns 1.213ns 1.989ns 1.203ns 1.531ns 2.206ns 1.202ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.378ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 142 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 45 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 142 -1 0 } } { "sd_control.v" "" { Text "C:/altera/quartus50/workone/sd_control.v" 45 -1 0 } }  } 0}  } { { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "7.761 ns" { sd_control:inst|block_num[9]~reg0 sd_control:inst|reduce_nor~402 sd_control:inst|reduce_nor~404 sd_control:inst|always2~3 sd_control:inst|cmd[44]~778 sd_control:inst|cmd[43] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.761 ns" { sd_control:inst|block_num[9]~reg0 sd_control:inst|reduce_nor~402 sd_control:inst|reduce_nor~404 sd_control:inst|always2~3 sd_control:inst|cmd[44]~778 sd_control:inst|cmd[43] } { 0.000ns 1.964ns 0.428ns 0.379ns 0.366ns 1.438ns } { 0.000ns 0.664ns 0.636ns 0.636ns 0.378ns 0.872ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "7.989 ns" { sd_clk_in mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|cmd[43] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.989 ns" { sd_clk_in sd_clk_in~combout mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|cmd[43] } { 0.000ns 0.000ns 2.146ns 2.206ns 1.194ns } { 0.000ns 1.100ns 0.664ns 0.000ns 0.679ns } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "13.611 ns" { sd_clk_in sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|block_num[9]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.611 ns" { sd_clk_in sd_clk_in~combout sd_clk_in~clkctrl initial_block:inst9|odd_division:clk_50m_25m|clk_odd initial_block:inst9|odd_division:clk_50m_25m|clk_odd~clkctrl initial_block:inst9|get_response:inst3|initial_done mux_2_1:inst16|out~8 mux_2_1:inst16|out~8clkctrl sd_control:inst|block_num[9]~reg0 } { 0.000ns 0.000ns 0.132ns 1.213ns 1.989ns 1.203ns 1.531ns 2.206ns 1.202ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.378ns 0.000ns 0.679ns } } }  } 0}