test.tan.qmsg

来自「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off test -c test --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off test -c test --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sd_clk_in " "Info: Assuming node \"sd_clk_in\" is an undefined clock" {  } { { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 56 40 208 72 "sd_clk_in" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sd_clk_in" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}