📄 mux_mib.tdf
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=8 LPM_WIDTH=5 LPM_WIDTHS=3 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ VERSION_END
-- Copyright (C) 1988-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 25
SUBDESIGN mux_mib
(
data[39..0] : input;
result[4..0] : output;
sel[2..0] : input;
)
VARIABLE
result_node[4..0] : WIRE;
sel_ffs_wire[2..0] : WIRE;
sel_node[2..0] : WIRE;
w_data347w[7..0] : WIRE;
w_data369w[3..0] : WIRE;
w_data370w[3..0] : WIRE;
w_data418w[7..0] : WIRE;
w_data440w[3..0] : WIRE;
w_data441w[3..0] : WIRE;
w_data487w[7..0] : WIRE;
w_data509w[3..0] : WIRE;
w_data510w[3..0] : WIRE;
w_data556w[7..0] : WIRE;
w_data578w[3..0] : WIRE;
w_data579w[3..0] : WIRE;
w_data625w[7..0] : WIRE;
w_data647w[3..0] : WIRE;
w_data648w[3..0] : WIRE;
w_result348w : WIRE;
w_result366w : WIRE;
w_result367w : WIRE;
w_result368w : WIRE;
w_result374w : WIRE;
w_result375w : WIRE;
w_result395w : WIRE;
w_result396w : WIRE;
w_result419w : WIRE;
w_result437w : WIRE;
w_result438w : WIRE;
w_result439w : WIRE;
w_result445w : WIRE;
w_result446w : WIRE;
w_result466w : WIRE;
w_result467w : WIRE;
w_result488w : WIRE;
w_result506w : WIRE;
w_result507w : WIRE;
w_result508w : WIRE;
w_result514w : WIRE;
w_result515w : WIRE;
w_result535w : WIRE;
w_result536w : WIRE;
w_result557w : WIRE;
w_result575w : WIRE;
w_result576w : WIRE;
w_result577w : WIRE;
w_result583w : WIRE;
w_result584w : WIRE;
w_result604w : WIRE;
w_result605w : WIRE;
w_result626w : WIRE;
w_result644w : WIRE;
w_result645w : WIRE;
w_result646w : WIRE;
w_result652w : WIRE;
w_result653w : WIRE;
w_result673w : WIRE;
w_result674w : WIRE;
w_sel371w[1..0] : WIRE;
w_sel442w[1..0] : WIRE;
w_sel511w[1..0] : WIRE;
w_sel580w[1..0] : WIRE;
w_sel649w[1..0] : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( w_result626w, w_result557w, w_result488w, w_result419w, w_result348w);
sel_ffs_wire[] = ( sel[2..0]);
sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]);
w_data347w[] = ( data[35..35], data[30..30], data[25..25], data[20..20], data[15..15], data[10..10], data[5..5], data[0..0]);
w_data369w[3..0] = w_data347w[3..0];
w_data370w[3..0] = w_data347w[7..4];
w_data418w[] = ( data[36..36], data[31..31], data[26..26], data[21..21], data[16..16], data[11..11], data[6..6], data[1..1]);
w_data440w[3..0] = w_data418w[3..0];
w_data441w[3..0] = w_data418w[7..4];
w_data487w[] = ( data[37..37], data[32..32], data[27..27], data[22..22], data[17..17], data[12..12], data[7..7], data[2..2]);
w_data509w[3..0] = w_data487w[3..0];
w_data510w[3..0] = w_data487w[7..4];
w_data556w[] = ( data[38..38], data[33..33], data[28..28], data[23..23], data[18..18], data[13..13], data[8..8], data[3..3]);
w_data578w[3..0] = w_data556w[3..0];
w_data579w[3..0] = w_data556w[7..4];
w_data625w[] = ( data[39..39], data[34..34], data[29..29], data[24..24], data[19..19], data[14..14], data[9..9], data[4..4]);
w_data647w[3..0] = w_data625w[3..0];
w_data648w[3..0] = w_data625w[7..4];
w_result348w = w_result366w;
w_result366w = ((sel_node[2..2] & w_result368w) # ((! sel_node[2..2]) & w_result367w));
w_result367w = w_result374w;
w_result368w = w_result395w;
w_result374w = (((w_data369w[1..1] & w_sel371w[0..0]) & (! w_result375w)) # (w_result375w & (w_data369w[3..3] # (! w_sel371w[0..0]))));
w_result375w = (((w_data369w[0..0] & (! w_sel371w[1..1])) & (! w_sel371w[0..0])) # (w_sel371w[1..1] & (w_sel371w[0..0] # w_data369w[2..2])));
w_result395w = (((w_data370w[1..1] & w_sel371w[0..0]) & (! w_result396w)) # (w_result396w & (w_data370w[3..3] # (! w_sel371w[0..0]))));
w_result396w = (((w_data370w[0..0] & (! w_sel371w[1..1])) & (! w_sel371w[0..0])) # (w_sel371w[1..1] & (w_sel371w[0..0] # w_data370w[2..2])));
w_result419w = w_result437w;
w_result437w = ((sel_node[2..2] & w_result439w) # ((! sel_node[2..2]) & w_result438w));
w_result438w = w_result445w;
w_result439w = w_result466w;
w_result445w = (((w_data440w[1..1] & w_sel442w[0..0]) & (! w_result446w)) # (w_result446w & (w_data440w[3..3] # (! w_sel442w[0..0]))));
w_result446w = (((w_data440w[0..0] & (! w_sel442w[1..1])) & (! w_sel442w[0..0])) # (w_sel442w[1..1] & (w_sel442w[0..0] # w_data440w[2..2])));
w_result466w = (((w_data441w[1..1] & w_sel442w[0..0]) & (! w_result467w)) # (w_result467w & (w_data441w[3..3] # (! w_sel442w[0..0]))));
w_result467w = (((w_data441w[0..0] & (! w_sel442w[1..1])) & (! w_sel442w[0..0])) # (w_sel442w[1..1] & (w_sel442w[0..0] # w_data441w[2..2])));
w_result488w = w_result506w;
w_result506w = ((sel_node[2..2] & w_result508w) # ((! sel_node[2..2]) & w_result507w));
w_result507w = w_result514w;
w_result508w = w_result535w;
w_result514w = (((w_data509w[1..1] & w_sel511w[0..0]) & (! w_result515w)) # (w_result515w & (w_data509w[3..3] # (! w_sel511w[0..0]))));
w_result515w = (((w_data509w[0..0] & (! w_sel511w[1..1])) & (! w_sel511w[0..0])) # (w_sel511w[1..1] & (w_sel511w[0..0] # w_data509w[2..2])));
w_result535w = (((w_data510w[1..1] & w_sel511w[0..0]) & (! w_result536w)) # (w_result536w & (w_data510w[3..3] # (! w_sel511w[0..0]))));
w_result536w = (((w_data510w[0..0] & (! w_sel511w[1..1])) & (! w_sel511w[0..0])) # (w_sel511w[1..1] & (w_sel511w[0..0] # w_data510w[2..2])));
w_result557w = w_result575w;
w_result575w = ((sel_node[2..2] & w_result577w) # ((! sel_node[2..2]) & w_result576w));
w_result576w = w_result583w;
w_result577w = w_result604w;
w_result583w = (((w_data578w[1..1] & w_sel580w[0..0]) & (! w_result584w)) # (w_result584w & (w_data578w[3..3] # (! w_sel580w[0..0]))));
w_result584w = (((w_data578w[0..0] & (! w_sel580w[1..1])) & (! w_sel580w[0..0])) # (w_sel580w[1..1] & (w_sel580w[0..0] # w_data578w[2..2])));
w_result604w = (((w_data579w[1..1] & w_sel580w[0..0]) & (! w_result605w)) # (w_result605w & (w_data579w[3..3] # (! w_sel580w[0..0]))));
w_result605w = (((w_data579w[0..0] & (! w_sel580w[1..1])) & (! w_sel580w[0..0])) # (w_sel580w[1..1] & (w_sel580w[0..0] # w_data579w[2..2])));
w_result626w = w_result644w;
w_result644w = ((sel_node[2..2] & w_result646w) # ((! sel_node[2..2]) & w_result645w));
w_result645w = w_result652w;
w_result646w = w_result673w;
w_result652w = (((w_data647w[1..1] & w_sel649w[0..0]) & (! w_result653w)) # (w_result653w & (w_data647w[3..3] # (! w_sel649w[0..0]))));
w_result653w = (((w_data647w[0..0] & (! w_sel649w[1..1])) & (! w_sel649w[0..0])) # (w_sel649w[1..1] & (w_sel649w[0..0] # w_data647w[2..2])));
w_result673w = (((w_data648w[1..1] & w_sel649w[0..0]) & (! w_result674w)) # (w_result674w & (w_data648w[3..3] # (! w_sel649w[0..0]))));
w_result674w = (((w_data648w[0..0] & (! w_sel649w[1..1])) & (! w_sel649w[0..0])) # (w_sel649w[1..1] & (w_sel649w[0..0] # w_data648w[2..2])));
w_sel371w[1..0] = sel_node[1..0];
w_sel442w[1..0] = sel_node[1..0];
w_sel511w[1..0] = sel_node[1..0];
w_sel580w[1..0] = sel_node[1..0];
w_sel649w[1..0] = sel_node[1..0];
END;
--VALID FILE
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