mux_bib.tdf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=2 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = lut 2 
SUBDESIGN mux_bib
( 
	data[3..0]	:	input;
	result[1..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[1..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data45w[1..0]	: WIRE;
	w_data59w[1..0]	: WIRE;
	w_result46w	: WIRE;
	w_result52w	: WIRE;
	w_result60w	: WIRE;
	w_result66w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result60w, w_result46w);
	sel_node[] = ( sel[0..0]);
	w_data45w[] = ( data[2..2], data[0..0]);
	w_data59w[] = ( data[3..3], data[1..1]);
	w_result46w = w_result52w;
	w_result52w = ((sel_node[] & w_data45w[1..1]) # ((! sel_node[]) & w_data45w[0..0]));
	w_result60w = w_result66w;
	w_result66w = ((sel_node[] & w_data59w[1..1]) # ((! sel_node[]) & w_data59w[0..0]));
END;
--VALID FILE