mux_sjb.tdf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=12 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


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--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.



--synthesis_resources = lut 12 
SUBDESIGN mux_sjb
( 
	data[23..0]	:	input;
	result[11..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[11..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data215w[1..0]	: WIRE;
	w_data229w[1..0]	: WIRE;
	w_data241w[1..0]	: WIRE;
	w_data253w[1..0]	: WIRE;
	w_data265w[1..0]	: WIRE;
	w_data277w[1..0]	: WIRE;
	w_data289w[1..0]	: WIRE;
	w_data301w[1..0]	: WIRE;
	w_data313w[1..0]	: WIRE;
	w_data325w[1..0]	: WIRE;
	w_data337w[1..0]	: WIRE;
	w_data349w[1..0]	: WIRE;
	w_result216w	: WIRE;
	w_result222w	: WIRE;
	w_result230w	: WIRE;
	w_result236w	: WIRE;
	w_result242w	: WIRE;
	w_result248w	: WIRE;
	w_result254w	: WIRE;
	w_result260w	: WIRE;
	w_result266w	: WIRE;
	w_result272w	: WIRE;
	w_result278w	: WIRE;
	w_result284w	: WIRE;
	w_result290w	: WIRE;
	w_result296w	: WIRE;
	w_result302w	: WIRE;
	w_result308w	: WIRE;
	w_result314w	: WIRE;
	w_result320w	: WIRE;
	w_result326w	: WIRE;
	w_result332w	: WIRE;
	w_result338w	: WIRE;
	w_result344w	: WIRE;
	w_result350w	: WIRE;
	w_result356w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result350w, w_result338w, w_result326w, w_result314w, w_result302w, w_result290w, w_result278w, w_result266w, w_result254w, w_result242w, w_result230w, w_result216w);
	sel_node[] = ( sel[0..0]);
	w_data215w[] = ( data[12..12], data[0..0]);
	w_data229w[] = ( data[13..13], data[1..1]);
	w_data241w[] = ( data[14..14], data[2..2]);
	w_data253w[] = ( data[15..15], data[3..3]);
	w_data265w[] = ( data[16..16], data[4..4]);
	w_data277w[] = ( data[17..17], data[5..5]);
	w_data289w[] = ( data[18..18], data[6..6]);
	w_data301w[] = ( data[19..19], data[7..7]);
	w_data313w[] = ( data[20..20], data[8..8]);
	w_data325w[] = ( data[21..21], data[9..9]);
	w_data337w[] = ( data[22..22], data[10..10]);
	w_data349w[] = ( data[23..23], data[11..11]);
	w_result216w = w_result222w;
	w_result222w = ((sel_node[] & w_data215w[1..1]) # ((! sel_node[]) & w_data215w[0..0]));
	w_result230w = w_result236w;
	w_result236w = ((sel_node[] & w_data229w[1..1]) # ((! sel_node[]) & w_data229w[0..0]));
	w_result242w = w_result248w;
	w_result248w = ((sel_node[] & w_data241w[1..1]) # ((! sel_node[]) & w_data241w[0..0]));
	w_result254w = w_result260w;
	w_result260w = ((sel_node[] & w_data253w[1..1]) # ((! sel_node[]) & w_data253w[0..0]));
	w_result266w = w_result272w;
	w_result272w = ((sel_node[] & w_data265w[1..1]) # ((! sel_node[]) & w_data265w[0..0]));
	w_result278w = w_result284w;
	w_result284w = ((sel_node[] & w_data277w[1..1]) # ((! sel_node[]) & w_data277w[0..0]));
	w_result290w = w_result296w;
	w_result296w = ((sel_node[] & w_data289w[1..1]) # ((! sel_node[]) & w_data289w[0..0]));
	w_result302w = w_result308w;
	w_result308w = ((sel_node[] & w_data301w[1..1]) # ((! sel_node[]) & w_data301w[0..0]));
	w_result314w = w_result320w;
	w_result320w = ((sel_node[] & w_data313w[1..1]) # ((! sel_node[]) & w_data313w[0..0]));
	w_result326w = w_result332w;
	w_result332w = ((sel_node[] & w_data325w[1..1]) # ((! sel_node[]) & w_data325w[0..0]));
	w_result338w = w_result344w;
	w_result344w = ((sel_node[] & w_data337w[1..1]) # ((! sel_node[]) & w_data337w[0..0]));
	w_result350w = w_result356w;
	w_result356w = ((sel_node[] & w_data349w[1..1]) # ((! sel_node[]) & w_data349w[0..0]));
END;
--VALID FILE