mux_lib.tdf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=4 LPM_WIDTH=9 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 18 
SUBDESIGN mux_lib
( 
	data[35..0]	:	input;
	result[8..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[8..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data310w[3..0]	: WIRE;
	w_data340w[3..0]	: WIRE;
	w_data365w[3..0]	: WIRE;
	w_data390w[3..0]	: WIRE;
	w_data415w[3..0]	: WIRE;
	w_data440w[3..0]	: WIRE;
	w_data465w[3..0]	: WIRE;
	w_data490w[3..0]	: WIRE;
	w_data515w[3..0]	: WIRE;
	w_result311w	: WIRE;
	w_result321w	: WIRE;
	w_result322w	: WIRE;
	w_result341w	: WIRE;
	w_result351w	: WIRE;
	w_result352w	: WIRE;
	w_result366w	: WIRE;
	w_result376w	: WIRE;
	w_result377w	: WIRE;
	w_result391w	: WIRE;
	w_result401w	: WIRE;
	w_result402w	: WIRE;
	w_result416w	: WIRE;
	w_result426w	: WIRE;
	w_result427w	: WIRE;
	w_result441w	: WIRE;
	w_result451w	: WIRE;
	w_result452w	: WIRE;
	w_result466w	: WIRE;
	w_result476w	: WIRE;
	w_result477w	: WIRE;
	w_result491w	: WIRE;
	w_result501w	: WIRE;
	w_result502w	: WIRE;
	w_result516w	: WIRE;
	w_result526w	: WIRE;
	w_result527w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result516w, w_result491w, w_result466w, w_result441w, w_result416w, w_result391w, w_result366w, w_result341w, w_result311w);
	sel_node[] = ( sel[1..0]);
	w_data310w[] = ( data[27..27], data[18..18], data[9..9], data[0..0]);
	w_data340w[] = ( data[28..28], data[19..19], data[10..10], data[1..1]);
	w_data365w[] = ( data[29..29], data[20..20], data[11..11], data[2..2]);
	w_data390w[] = ( data[30..30], data[21..21], data[12..12], data[3..3]);
	w_data415w[] = ( data[31..31], data[22..22], data[13..13], data[4..4]);
	w_data440w[] = ( data[32..32], data[23..23], data[14..14], data[5..5]);
	w_data465w[] = ( data[33..33], data[24..24], data[15..15], data[6..6]);
	w_data490w[] = ( data[34..34], data[25..25], data[16..16], data[7..7]);
	w_data515w[] = ( data[35..35], data[26..26], data[17..17], data[8..8]);
	w_result311w = w_result321w;
	w_result321w = (((w_data310w[1..1] & sel_node[0..0]) & (! w_result322w)) # (w_result322w & (w_data310w[3..3] # (! sel_node[0..0]))));
	w_result322w = (((w_data310w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data310w[2..2])));
	w_result341w = w_result351w;
	w_result351w = (((w_data340w[1..1] & sel_node[0..0]) & (! w_result352w)) # (w_result352w & (w_data340w[3..3] # (! sel_node[0..0]))));
	w_result352w = (((w_data340w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data340w[2..2])));
	w_result366w = w_result376w;
	w_result376w = (((w_data365w[1..1] & sel_node[0..0]) & (! w_result377w)) # (w_result377w & (w_data365w[3..3] # (! sel_node[0..0]))));
	w_result377w = (((w_data365w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data365w[2..2])));
	w_result391w = w_result401w;
	w_result401w = (((w_data390w[1..1] & sel_node[0..0]) & (! w_result402w)) # (w_result402w & (w_data390w[3..3] # (! sel_node[0..0]))));
	w_result402w = (((w_data390w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data390w[2..2])));
	w_result416w = w_result426w;
	w_result426w = (((w_data415w[1..1] & sel_node[0..0]) & (! w_result427w)) # (w_result427w & (w_data415w[3..3] # (! sel_node[0..0]))));
	w_result427w = (((w_data415w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data415w[2..2])));
	w_result441w = w_result451w;
	w_result451w = (((w_data440w[1..1] & sel_node[0..0]) & (! w_result452w)) # (w_result452w & (w_data440w[3..3] # (! sel_node[0..0]))));
	w_result452w = (((w_data440w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data440w[2..2])));
	w_result466w = w_result476w;
	w_result476w = (((w_data465w[1..1] & sel_node[0..0]) & (! w_result477w)) # (w_result477w & (w_data465w[3..3] # (! sel_node[0..0]))));
	w_result477w = (((w_data465w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data465w[2..2])));
	w_result491w = w_result501w;
	w_result501w = (((w_data490w[1..1] & sel_node[0..0]) & (! w_result502w)) # (w_result502w & (w_data490w[3..3] # (! sel_node[0..0]))));
	w_result502w = (((w_data490w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data490w[2..2])));
	w_result516w = w_result526w;
	w_result526w = (((w_data515w[1..1] & sel_node[0..0]) & (! w_result527w)) # (w_result527w & (w_data515w[3..3] # (! sel_node[0..0]))));
	w_result527w = (((w_data515w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data515w[2..2])));
END;
--VALID FILE