mux_cib.tdf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=3 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


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--synthesis_resources = lut 3 
SUBDESIGN mux_cib
( 
	data[5..0]	:	input;
	result[2..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[2..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data68w[1..0]	: WIRE;
	w_data82w[1..0]	: WIRE;
	w_data94w[1..0]	: WIRE;
	w_result101w	: WIRE;
	w_result69w	: WIRE;
	w_result75w	: WIRE;
	w_result83w	: WIRE;
	w_result89w	: WIRE;
	w_result95w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result95w, w_result83w, w_result69w);
	sel_node[] = ( sel[0..0]);
	w_data68w[] = ( data[3..3], data[0..0]);
	w_data82w[] = ( data[4..4], data[1..1]);
	w_data94w[] = ( data[5..5], data[2..2]);
	w_result101w = ((sel_node[] & w_data94w[1..1]) # ((! sel_node[]) & w_data94w[0..0]));
	w_result69w = w_result75w;
	w_result75w = ((sel_node[] & w_data68w[1..1]) # ((! sel_node[]) & w_data68w[0..0]));
	w_result83w = w_result89w;
	w_result89w = ((sel_node[] & w_data82w[1..1]) # ((! sel_node[]) & w_data82w[0..0]));
	w_result95w = w_result101w;
END;
--VALID FILE