decode_9oa.tdf

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_DECODES=8 LPM_WIDTH=3 data enable eq
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_mgl 2005:04:13:17:26:48:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END


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--synthesis_resources = lut 8 
SUBDESIGN decode_9oa
( 
	data[2..0]	:	input;
	enable	:	input;
	eq[7..0]	:	output;
) 
VARIABLE 
	data_wire[2..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[7..0]	: WIRE;
	eq_wire[7..0]	: WIRE;
	w_anode404w[3..0]	: WIRE;
	w_anode421w[3..0]	: WIRE;
	w_anode431w[3..0]	: WIRE;
	w_anode441w[3..0]	: WIRE;
	w_anode451w[3..0]	: WIRE;
	w_anode461w[3..0]	: WIRE;
	w_anode471w[3..0]	: WIRE;
	w_anode481w[3..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[7..0] = eq_wire[7..0];
	eq_wire[] = ( w_anode481w[3..3], w_anode471w[3..3], w_anode461w[3..3], w_anode451w[3..3], w_anode441w[3..3], w_anode431w[3..3], w_anode421w[3..3], w_anode404w[3..3]);
	w_anode404w[] = ( (w_anode404w[2..2] & (! data_wire[2..2])), (w_anode404w[1..1] & (! data_wire[1..1])), (w_anode404w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode421w[] = ( (w_anode421w[2..2] & (! data_wire[2..2])), (w_anode421w[1..1] & (! data_wire[1..1])), (w_anode421w[0..0] & data_wire[0..0]), enable_wire);
	w_anode431w[] = ( (w_anode431w[2..2] & (! data_wire[2..2])), (w_anode431w[1..1] & data_wire[1..1]), (w_anode431w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode441w[] = ( (w_anode441w[2..2] & (! data_wire[2..2])), (w_anode441w[1..1] & data_wire[1..1]), (w_anode441w[0..0] & data_wire[0..0]), enable_wire);
	w_anode451w[] = ( (w_anode451w[2..2] & data_wire[2..2]), (w_anode451w[1..1] & (! data_wire[1..1])), (w_anode451w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode461w[] = ( (w_anode461w[2..2] & data_wire[2..2]), (w_anode461w[1..1] & (! data_wire[1..1])), (w_anode461w[0..0] & data_wire[0..0]), enable_wire);
	w_anode471w[] = ( (w_anode471w[2..2] & data_wire[2..2]), (w_anode471w[1..1] & data_wire[1..1]), (w_anode471w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode481w[] = ( (w_anode481w[2..2] & data_wire[2..2]), (w_anode481w[1..1] & data_wire[1..1]), (w_anode481w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE