test.fit.qmsg

来自「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）」· QMSG 代码 · 共 22 行 · 第 1/5 页

{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C20F484C8 " "Info: Device EP2C20F484C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C8 " "Info: Device EP2C50F484C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sd_clk_in (placed in PIN A12 (CLK9, LVDSCLK4p, Input)) " "Info: Automatically promoted node sd_clk_in (placed in PIN A12 (CLK9, LVDSCLK4p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G10 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G10" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mux_2_1:inst16\|out~8 " "Info: Destination node mux_2_1:inst16\|out~8" {  } { { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mux_2_1:inst16\|out~8" } } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { mux_2_1:inst16|out~8 } "NODE_NAME" } "" } } { "C:/altera/quartus50/workone/test.fld" "" { Floorplan "C:/altera/quartus50/workone/test.fld" "" "" { mux_2_1:inst16|out~8 } "NODE_NAME" } }  } 0}  } {  } 0}  } { { "test.bdf" "" { Schematic "C:/altera/quartus50/workone/test.bdf" { { 56 40 208 72 "sd_clk_in" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sd_clk_in" } } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { sd_clk_in } "NODE_NAME" } "" } } { "C:/altera/quartus50/workone/test.fld" "" { Floorplan "C:/altera/quartus50/workone/test.fld" "" "" { sd_clk_in } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd  " "Info: Automatically promoted node initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mux_2_1:inst16\|out~8 " "Info: Destination node mux_2_1:inst16\|out~8" {  } { { "mux_2_1.v" "" { Text "C:/altera/quartus50/workone/mux_2_1.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mux_2_1:inst16\|out~8" } } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { mux_2_1:inst16|out~8 } "NODE_NAME" } "" } } { "C:/altera/quartus50/workone/test.fld" "" { Floorplan "C:/altera/quartus50/workone/test.fld" "" "" { mux_2_1:inst16|out~8 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd~3 " "Info: Destination node initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd~3" {  } { { "odd_division.v" "" { Text "C:/altera/quartus50/workone/odd_division.v" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd~3" } } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { initial_block:inst9|odd_division:clk_50m_25m|clk_odd~3 } "NODE_NAME" } "" } } { "C:/altera/quartus50/workone/test.fld" "" { Floorplan "C:/altera/quartus50/workone/test.fld" "" "" { initial_block:inst9|odd_division:clk_50m_25m|clk_odd~3 } "NODE_NAME" } }  } 0}  } {  } 0}  } { { "odd_division.v" "" { Text "C:/altera/quartus50/workone/odd_division.v" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "initial_block:inst9\|odd_division:clk_50m_25m\|clk_odd" } } } } { "C:/altera/quartus50/workone/db/test_cmp.qrpt" "" { Report "C:/altera/quartus50/workone/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/altera/quartus50/workone/db/test.quartus_db" { Floorplan "C:/altera/quartus50/workone/" "" "" { initial_block:inst9|odd_division:clk_50m_25m|clk_odd } "NODE_NAME" } "" } } { "C:/altera/quartus50/workone/test.fld" "" { Floorplan "C:/altera/quartus50/workone/test.fld" "" "" { initial_block:inst9|odd_division:clk_50m_25m|clk_odd } "NODE_NAME" } }  } 0}